URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [sim/] [testbenches/] [xml/] [vga_char_ctrl_def_duth.design.xml] - Diff between revs 133 and 135

-Rev 133
+Rev 135
 Line 4...
 // Generated File Do Not EDIT                                                                         //
 //                                                                                                    //
 // ./tools/verilog/gen_tb -vendor opencores.org -library logic  -component vga_char_ctrl  -version def //
 //                                                                                                    //
 -->
-xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
 xmlns:socgen="http://opencores.org"
 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
-xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
+xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
-http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 opencores.org
 logic
 vga_char_ctrl
 def_duth.design
 add_h_load
 add_l_load
 address
 ascii_load
 back_color
 blue_pad_out
 char_color
 clk
 cursor_color
 green_pad_out
 hsync_n_pad_out
 red_pad_out
 reset
 vsync_n_pad_out
 wdata
 dut
  CHARACTER_DECODE_DELAY
  H_ACTIVE
  H_BACK_PORCH
  H_FRONT_PORCH
  H_SYNCH
  H_TOTAL
  V_ACTIVE
  V_BACK_PORCH
  V_FRONT_PORCH
  V_SYNCH
  V_TOTAL
+ CHAR_RAM_ADDR
+ CHAR_RAM_WIDTH
+ CHAR_RAM_WORDS
+ CHAR_RAM_WRITETHRU