URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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wishbone
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wishbone
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model
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model
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monitor default
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monitor
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fs-sim
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dest_dir../verilog/sim/
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verilogSourcelibraryDir
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verilog
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verilog
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model_monitor
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ADD_WIDTH
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8
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DATAWIDTH
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32
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fs-sim
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fs-syn
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dest_dir../verilog/syn/
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verilogSourcelibraryDir
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rtl
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verilog:Kactus2:
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verilog
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TEST_NAME"unspecified"
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INSTANCE"none"
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ADD_WIDTH32
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DATA_WIDTH32
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clk
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wire
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in
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reset
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wire
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in
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wb_adr
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wire
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in
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ADD_WIDTH-10
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wb_ack
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wire
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in
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wb_err
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wire
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in
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wb_cyc
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wire
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in
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wb_stb
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wire
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in
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wb_we
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TEST_NAME"unspecified"
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wire
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INSTANCE"none"
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in
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ADD_WIDTH32
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DATA_WIDTH32
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clk
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wb_read
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wire
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wire
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in
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in
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DATA_WIDTH-10
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reset
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wb_write
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wire
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wire
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in
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in
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DATA_WIDTH-10
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wb_adr
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wire
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in
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ADD_WIDTH-10
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wb_ack
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wb_sel
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wire
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wire
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in
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in
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30
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wb_err
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wire
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in
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wb_cyc
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wire
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in
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wb_stb
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wire
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in
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wb_we
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wire
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in
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fs-sim
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wb_read
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wire
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dest_dir../verilog/sim/
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in
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verilogSourcelibraryDir
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DATA_WIDTH-10
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wb_write
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wire
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in
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DATA_WIDTH-10
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wb_sel
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wire
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in
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30
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fs-syn
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dest_dir../verilog/syn/
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verilogSourcelibraryDir
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