URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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// Generated File Do Not EDIT //
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// Generated File Do Not EDIT //
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// //
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// //
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// ./tools/verilog/gen_tb -vendor opencores.org -library wishbone -component wb_memory -version def //
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// ./tools/verilog/gen_tb -vendor opencores.org -library wishbone -component wb_memory -version def //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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wishbone
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wishbone
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wb_memory
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wb_memory
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def_duth.design
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def_duth.design
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ack_o
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ack_o
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adr_i
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adr_i
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clk_i
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clk_i
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cyc_i
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cyc_i
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dat_i
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dat_i
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dat_o
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dat_o
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rst_i
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rst_i
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sel_i
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sel_i
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stb_i
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stb_i
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we_i
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we_i
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dut
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dut
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SRAM_MEM_0_FILE
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SRAM_MEM_0_FILE
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SRAM_MEM_1_FILE
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SRAM_MEM_1_FILE
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SRAM_MEM_2_FILE
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SRAM_MEM_2_FILE
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SRAM_MEM_3_FILE
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SRAM_MEM_3_FILE
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adr_width
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adr_width
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dat_width
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dat_width
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mem_size
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mem_size
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wb_addr_width
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wb_addr_width
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wb_byte_lanes
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wb_byte_lanes
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wb_data_width
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wb_data_width
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