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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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Testbench
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Testbench
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clock_gen
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clock_gen
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def default
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def
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master_clk
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master_clk
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clk
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clk
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wire
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clk
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clk
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wire
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master_reset
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reset
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reset
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reg
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master_reset
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gen_verilog_sim
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104.0
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none
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:*Simulation:*
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./tools/verilog/gen_verilog
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destination
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clock_gen_def
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gen_verilog_syn
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104.0
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none
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:*Synthesis:*
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./tools/verilog/gen_verilog
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destination
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clock_gen_def
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reset
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reset
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reg
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gen_verilog_sim
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104.0
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none
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:*Simulation:*
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tools/verilog/gen_verilog
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destination
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clock_gen_def
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gen_verilog_syn
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104.0
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none
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:*Synthesis:*
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tools/verilog/gen_verilog
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destination
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clock_gen_def
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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doc
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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STOP_WIDTH1
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BAD_WIDTH1
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START
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wire
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in
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STOP
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wire
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inSTOP_WIDTH-10
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BAD
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wire
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inBAD_WIDTH-10
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FAIL
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reg
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out
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FINISH
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reg
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out
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verilog
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verilog
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clock_gen_def
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STOP_WIDTH
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1
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BAD_WIDTH
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1
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fs-sim
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rtl
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verilog:Kactus2:
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verilog
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verilog
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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doc
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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fs-sim
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../verilog/clock_gen_sim
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verilogSourcefragment
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STOP_WIDTH1
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BAD_WIDTH1
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../verilog/copyright
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verilogSourceinclude
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../verilog/sim/clock_gen_def
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verilogSourcemodule
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clk
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dest_dir
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../views/sim/
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wire
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verilogSourcelibraryDir
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in
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reset
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reg
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out
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fs-syn
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START
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../verilog/clock_gen_syn
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wire
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verilogSourcefragment
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in
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STOP
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wire
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inSTOP_WIDTH-10
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BAD
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../verilog/copyright
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wire
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verilogSourceinclude
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inBAD_WIDTH-10
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FAIL
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../verilog/syn/clock_gen_def
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reg
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verilogSourcemodule
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out
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FINISH
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dest_dir
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../views/syn/
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reg
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verilogSourcelibraryDir
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out
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fs-common
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fs-sim
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../verilog/clock_gen_sim
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verilogSourcefragment
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../verilog/copyright
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verilogSourceinclude
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../verilog/sim/clock_gen_def
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verilogSourcemodule
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dest_dir
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../views/sim/
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verilogSourcelibraryDir
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fs-syn
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../verilog/clock_gen_syn
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verilogSourcefragment
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../verilog/copyright
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verilogSourceinclude
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../verilog/syn/clock_gen_def
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verilogSourcemodule
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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