| Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
|
// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
Testbench
|
Testbench
|
mt45w8mw12
|
mt45w8mw12
|
def default
|
def
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_sim
|
gen_verilog_sim
|
104.0
|
104.0
|
none
|
none
|
:*Simulation:*
|
:*Simulation:*
|
./tools/verilog/gen_verilog
|
tools/verilog/gen_verilog
|
|
|
|
|
destination
|
destination
|
mt45w8mw12_def
|
mt45w8mw12_def
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_syn
|
gen_verilog_syn
|
104.0
|
104.0
|
none
|
none
|
:*Synthesis:*
|
:*Synthesis:*
|
./tools/verilog/gen_verilog
|
tools/verilog/gen_verilog
|
|
|
|
|
destination
|
destination
|
mt45w8mw12_def
|
mt45w8mw12_def
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
verilog
|
|
verilog
|
spirit:library="Testbench"
|
mt45w8mw12_def
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
ADDR_BITS
|
|
23
|
|
|
|
|
|
DQ_BITS
|
|
16
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
rtl
|
|
verilog:Kactus2:
|
|
verilog
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
ADDR_BITS23
|
|
DQ_BITS16
|
|
MEM_BITS16
|
|
|
|
|
|
|
|
|
|
clk
|
|
wire
|
sim:*Simulation:*
|
in
|
|
|
|
|
|
adv_n
|
Verilog
|
wire
|
|
in
|
|
|
fs-sim
|
|
|
|
|
|
|
cre
|
|
wire
|
syn:*Synthesis:*
|
in
|
|
|
|
|
|
o_wait
|
Verilog
|
wire
|
|
out
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
ce_n
|
|
wire
|
doc
|
in
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
oe_n
|
|
wire
|
|
in
|
|
|
|
|
|
we_n
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
ADDR_BITS23
|
|
DQ_BITS16
|
|
MEM_BITS16
|
|
|
|
|
lb_n
|
|
wire
|
|
in
|
|
|
|
|
|
ub_n
|
clk
|
wire
|
wire
|
in
|
in
|
|
|
|
|
addr
|
adv_n
|
wire
|
wire
|
in
|
in
|
ADDR_BITS-10
|
|
|
|
|
|
|
cre
|
|
wire
|
|
in
|
|
|
|
|
dq
|
o_wait
|
wire
|
wire
|
inout
|
out
|
DQ_BITS-10
|
|
|
|
|
|
|
|
|
ce_n
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
oe_n
|
|
wire
|
|
in
|
|
|
|
|
|
we_n
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
lb_n
|
|
wire
|
|
in
|
|
|
|
|
|
ub_n
|
|
wire
|
|
in
|
|
|
|
|
|
addr
|
|
wire
|
|
in
|
|
ADDR_BITS-10
|
|
|
|
|
|
|
|
dq
|
|
wire
|
|
inout
|
|
DQ_BITS-10
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/top.sim
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/sim/mt45w8mw12_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
dest_dir../views/sim/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
fs-syn
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
../verilog/copyright
|
../verilog/top.sim
|
verilogSourceinclude
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
../verilog/top.syn
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
../verilog/sim/mt45w8mw12_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
../verilog/syn/mt45w8mw12_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
dest_dir../views/syn/
|
dest_dir../views/sim/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/top.syn
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/syn/mt45w8mw12_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
dest_dir../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
