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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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Testbench
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Testbench
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toolflow
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toolflow
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icarus
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icarus
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gen_elab_filelists
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gen_elab_filelists
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104.0
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104.0
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none
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none
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:*Simulation:*
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:*Simulation:*
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:*Synthesis:*
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:*Synthesis:*
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./tools/sys/gen_elab_child_filelist
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tools/sys/gen_elab_child_filelist
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top_file
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top_file
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./TestBench
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./TestBench
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top
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top
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gen_filelists
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gen_filelists
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104.0
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104.0
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none
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none
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:*Simulation:*
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:*Simulation:*
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:*Synthesis:*
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:*Synthesis:*
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./tools/sys/gen_child_filelist
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tools/sys/gen_child_filelist
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top_file
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top_file
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./TestBench
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./TestBench
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top
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top
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gen_cov_filelist
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gen_cov_filelist
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104.0
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104.0
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none
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none
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:*Lint:*
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:*Lint:*
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./tools/sys/gen_child_filelist
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tools/sys/gen_child_filelist
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top_file
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top_file
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"-v ./TestBench"
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"-v ./TestBench"
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top
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top
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suffix
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suffix
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COV
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COV
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leader
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leader
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"-v "
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"-v "
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gen_verilogLib_sim
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105.0
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none
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:*Simulation:*
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./tools/verilog/gen_verilogLib
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view
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sim
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gen_verilogLib_syn
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105.0
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none
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:*Synthesis:*
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./tools/verilog/gen_verilogLib
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view
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syn
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gen_verilogLib_lint
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gen_verilogLib_sim
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105.0
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105.0
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none
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none
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:*Lint:*
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:*Simulation:*
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./tools/verilog/gen_verilogLib
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tools/verilog/gen_verilogLib
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view
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view
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lint
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sim
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gen_verilogLib_syn
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105.0
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none
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:*Synthesis:*
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tools/verilog/gen_verilogLib
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view
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syn
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gen_verilogLib_lint
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105.0
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none
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:*Lint:*
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tools/verilog/gen_verilogLib
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view
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lint
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fs-sim
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dest_dir
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../views/sim/
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verilogSource
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libraryDir
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fs-sim
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dest_dir
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../views/sim/
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verilogSource
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libraryDir
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fs-syn
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dest_dir
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../views/syn/
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verilogSource
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libraryDir
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fs-syn
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fs-lint
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dest_dir
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../views/syn/
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verilogSource
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libraryDir
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dest_dir
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../views/lint/
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verilogSource
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libraryDir
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fs-lint
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dest_dir
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../views/lint/
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verilogSource
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libraryDir
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PERIOD40
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TIMEOUT100000
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PERIOD40
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TIMEOUT100000
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Bfm
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spirit:library="Testbench"
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spirit:name="clock_gen"
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spirit:version="bfm.design"/>
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Bfm
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sim
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:*Simulation:*
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Verilog
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fs-sim
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syn
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:*Synthesis:*
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Verilog
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fs-syn
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Bfm
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Bfm
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lint
|
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:*Lint:*
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Verilog
|
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fs-lint
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sim
|
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:*Simulation:*
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Verilog
|
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fs-sim
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|
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|
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syn
|
|
:*Synthesis:*
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Verilog
|
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fs-syn
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|
|
|
|
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lint
|
|
:*Lint:*
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Verilog
|
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fs-lint
|
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clk
|
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wire
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in
|
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START
|
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wire
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in
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FAIL
|
|
wire
|
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out
|
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FINISH
|
clk
|
wire
|
wire
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out
|
in
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START
|
|
wire
|
|
in
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FAIL
|
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wire
|
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out
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FINISH
|
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wire
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out
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