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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilog.xml] - Diff between revs 134 and 135

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Rev 134 Rev 135
Line 25... Line 25...
//   You should have received a copy of the GNU Lesser General            //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
//                                                                        //
-->
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
Testbench
Testbench
toolflow
toolflow
verilog
verilog
 
 
 
 
 
 
 
 
 
 
  gen_verilogLib_sim
  gen_verilogLib_sim
  105.0
  105.0
  none
  none
  :*Simulation:*
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
  tools/verilog/gen_verilogLib
    
    
    
    
      view
      view
      sim
      sim
    
    
  
  
 
 
 
 
 
 
 
 
 
 
  gen_verilogLib_syn
  gen_verilogLib_syn
  105.0
  105.0
  none
  none
  :*Synthesis:*
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
  tools/verilog/gen_verilogLib
    
    
    
    
      view
      view
      syn
      syn
    
    
  
  
 
 
 
 
 
 
 
 
 
 
 
 
Line 81... Line 81...
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
   
      fs-sim
      fs-sim
 
 
      
      
        dest_dir
        dest_dir
        ../views/sim/
        ../views/sim/
        verilogSource
        verilogSource
        libraryDir
        libraryDir
      
      
 
 
   
   
 
 
 
 
 
 
   
   
      fs-syn
      fs-syn
 
 
      
      
        dest_dir
        dest_dir
        ../views/syn/
        ../views/syn/
        verilogSource
        verilogSource
        libraryDir
        libraryDir
      
      
 
 
   
   
 
 
 
 
   
   
      fs-lint
      fs-lint
 
 
      
      
        dest_dir
        dest_dir
        ../views/syn/
        ../views/syn/
        verilogSource
        verilogSource
        libraryDir
        libraryDir
      
      
 
 
   
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
       
       
 
 
 
 
 
 
 
 
              
              
              sim
              sim
              :*Simulation:*
              :*Simulation:*
              Verilog
              Verilog
              
              
              fs-sim
              fs-sim
              
              
 
 
 
 
              
              
              syn
              syn
              :*Synthesis:*
              :*Synthesis:*
              Verilog
              Verilog
              
              
              fs-syn
              fs-syn
              
              
 
 
 
 
 
 
              
              
              lint
              lint
              :*Lint:*
              :*Lint:*
              Verilog
              Verilog
              
              
              fs-lint
              fs-lint
              
              
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
      
      
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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