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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_sync.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
Line 1...	Line 1...



`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`cde`	`cde`
`jtag`	`jtag`
`sync default`	`sync`





`jtag`	`jtag`





`clk`
`jtag_clk`



`test_logic_reset`
`test_logic_reset`



`capture_dr`
`capture_dr`



`shift_dr`
`shift_dr`



`update_dr`
`update_dr`



	`clk`
	`jtag_clk`



`tdi`	`test_logic_reset`
`tdi`	`test_logic_reset`



`tdo`	`capture_dr`
`tdo`	`capture_dr`



`select`	`shift_dr`
`select`	`shift_dr`



	`update_dr`
	`update_dr`




	`tdi`
	`tdi`



	`tdo`
	`tdo`



	`select`
	`select`


`syn_jtag`







`clk`
`syn_clk`



`capture_dr`
`syn_capture_dr`



`shift_dr`
`syn_shift_dr`



`update_dr`
`syn_update_dr`




`tdi`
`syn_tdi`



`tdo`
`syn_tdo`



`select`
`syn_select`


	`syn_jtag`


















`gen_verilog`	`clk`
`104.0`	`syn_clk`
`none`
`common`
`./tools/verilog/gen_verilog`


`destination`
`jtag_sync`





	`capture_dr`
	`syn_capture_dr`



	`shift_dr`
	`syn_shift_dr`



	`update_dr`
	`syn_update_dr`





	`tdi`
	`syn_tdi`



	`tdo`
	`syn_tdo`



	`select`
	`syn_select`







`verilog`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="verilog"/>`









`commoncommon`
`Verilog`


`fs-common`









`sim:Simulation:`
`Verilog`


`fs-sim`




`syn:Synthesis:`
`Verilog`


`fs-syn`







`doc`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="documentation"/>`

`:Documentation:`
`Verilog`




	`gen_verilog`
	`104.0`
	`none`
	`:common:`
	`tools/verilog/gen_verilog`


	`destination`
	`jtag_sync`

















`clk`
`wire`	`verilog`
`in`

	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="verilog"/>`









	`common:common:`
	`Verilog`


	`fs-common`







	`sim:Simulation:`
	`Verilog`


	`fs-sim`




	`syn:Synthesis:`
	`Verilog`


	`fs-syn`







`fs-sim`	`doc`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="documentation"/>`

	`:Documentation:`
	`Verilog`




`../verilog/sync`
`verilogSourcefragment`





`../verilog/copyright`
`verilogSourceinclude`









`fs-sim`



`dest_dir`
`../verilog/`
`verilogSource`
`libraryDir`


	`clk`
	`wire`
	`in`



	`jtag_clk`
`fs-syn`	`wire`
	`in`


	`test_logic_reset`
`dest_dir`	`wire`
`../verilog/`	`in`
`verilogSource`
`libraryDir`



	`capture_dr`
	`wire`
	`in`




	`shift_dr`
	`wire`
	`in`




`fs-lint`	`update_dr`
	`wire`
`dest_dir`	`in`
`../verilog/`
`verilogSource`
`libraryDir`


	`tdi`
	`wire`
	`in`


	`tdo`
	`wire`
	`out`


	`select`
	`wire`
	`in`





	`syn_clk`
	`wire`
	`out`


	`syn_capture_dr`
	`wire`
	`out`


	`syn_shift_dr`
	`wire`
	`out`



	`syn_update_dr`
	`wire`
	`out`


	`syn_tdi`
	`wire`
	`out`



	`syn_tdo`
	`wire`
	`in`


	`syn_select`
	`wire`
	`out`



















	`fs-sim`



	`../verilog/sync`
	`verilogSourcefragment`





	`../verilog/copyright`
	`verilogSourceinclude`





	`dest_dir`
	`../verilog/`
	`verilogSource`
	`libraryDir`










	`fs-syn`


	`dest_dir`
	`../verilog/`
	`verilogSource`
	`libraryDir`









	`fs-lint`

	`dest_dir`
	`../verilog/`
	`verilogSource`
	`libraryDir`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_sync.xml] - Diff between revs 134 and 135