URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [jtag_tap_dutg.design.xml] - Diff between revs 133 and 135

-Rev 133
+Rev 135
 Line 4...
 // Generated File Do Not EDIT                     //
 //                                                //
 // regen by adding -tb to gen_verilog script      //
 //                                                //
 -->
-xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
 xmlns:socgen="http://opencores.org"
 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
-xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
+xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
-http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 opencores.org
 cde
 jtag
 tap_dutg.design
 bsr_output_mode
 bsr_select_o
 bsr_tdo_i
 capture_dr_o
 jtag_clk
 select_o
 aux_select_o
 shift_dr_o
 shiftcapture_dr_clk_o
 tap_highz_mode
 tclk_pad_in
 tdi_o
 tdi_pad_in
 tdo_i
 aux_tdo_i
 tdo_pad_oe
 tdo_pad_out
 test_logic_reset_o
 tms_pad_in
 trst_n_pad_in
 update_dr_clk_o
 update_dr_o
 dut
  INST_LENGTH
  INST_RETURN
  EXTEST
  SAMPLE
  HIGHZ_MODE
  CHIP_ID_ACCESS
  CLAMP
  RPC_DATA
  RPC_ADD
  BYPASS
  CHIP_ID_VAL