OpenCores
URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwram.vhd] - Diff between revs 2 and 7

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 2 Rev 7
Line 1... Line 1...
--
--
--  Synchronous dual-port RAM with separate clocks for read and write ports.
--  Synchronous two-port RAM with separate clocks for read and write ports.
--  The synthesizer for Xilinx Spartan-3 will infer Block RAM for this entity.
--  The synthesizer for Xilinx Spartan-3 will infer Block RAM for this entity.
--
--
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.