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[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwstream.vhd] - Diff between revs 2 and 3

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--  spwrecvfront implementations. It also implements a receive FIFO and
--  spwrecvfront implementations. It also implements a receive FIFO and
--  a transmit FIFO.
--  a transmit FIFO.
--
--
--  The SpaceWire standard requires that each transceiver use an initial
--  The SpaceWire standard requires that each transceiver use an initial
--  signalling rate of 10 Mbit/s. This implies that the system clock frequency
--  signalling rate of 10 Mbit/s. This implies that the system clock frequency
--  must be a multiple of 10 MHz. See the datasheet for further details on
--  must be a multiple of 10 MHz. See the manual for further details on
--  bitrates and clocking.
--  bitrates and clocking.
--
--
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
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    generic (
    generic (
        -- System clock frequency in Hz.
        -- System clock frequency in Hz.
        -- This must be set to the frequency of "clk". It is used to setup
        -- This must be set to the frequency of "clk". It is used to setup
        -- counters for reset timing, disconnect timeout and to transmit
        -- counters for reset timing, disconnect timeout and to transmit
        -- at 10 Mbit/s during the handshake.
        -- at 10 Mbit/s during the link handshake.
        sysfreq:        real;
        sysfreq:        real;
 
 
 
        -- Transmit clock frequency in Hz (only if tximpl = impl_fast).
 
        -- This must be set to the frequency of "txclk". It is used to
 
        -- transmit at 10 Mbit/s during the link handshake.
 
        txclkfreq:      real := 0.0;
 
 
        -- Selection of a receiver front-end implementation.
        -- Selection of a receiver front-end implementation.
        rximpl:         spw_implementation_type := impl_generic;
        rximpl:         spw_implementation_type := impl_generic;
 
 
        -- Maximum number of bits received per system clock
        -- Maximum number of bits received per system clock
        -- (must be 1 in case of impl_generic).
        -- (must be 1 in case of impl_generic).
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        -- Enables link start once the Ready state is reached.
        -- Enables link start once the Ready state is reached.
        -- Without autostart or linkstart, the link remains in state Ready.
        -- Without autostart or linkstart, the link remains in state Ready.
        linkstart:  in  std_logic;
        linkstart:  in  std_logic;
 
 
        -- Do not start link (overrides linkstart and autostart) and/or disconnect
        -- Do not start link (overrides linkstart and autostart) and/or
        -- if the link is in state Run.
        -- disconnect a running link.
        linkdis:    in  std_logic;
        linkdis:    in  std_logic;
 
 
        -- Scaling factor minus 1, used to scale the system clock into the transmission
        -- Scaling factor minus 1, used to scale the transmit base clock into
        -- signalling rate. The system clock is divided by (unsigned(divcnt) + 1).
        -- the transmission bit rate. The system clock (for impl_generic) or
 
        -- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1).
        -- Changing this signal will immediately change the transmission rate.
        -- Changing this signal will immediately change the transmission rate.
        -- During link setup, the transmission rate is always 10 Mbit/s.
        -- During link setup, the transmission rate is always 10 Mbit/s.
        txdivcnt:   in  std_logic_vector(7 downto 0);
        txdivcnt:   in  std_logic_vector(7 downto 0);
 
 
        -- High for one clock cycle to request transmission of a TimeCode.
        -- High for one clock cycle to request transmission of a TimeCode.
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    -- Disconnect time (850 ns) in system clocks
    -- Disconnect time (850 ns) in system clocks
    constant disconnect_time:   integer := integer(sysfreq * 850.0e-9);
    constant disconnect_time:   integer := integer(sysfreq * 850.0e-9);
 
 
    -- Initial tx clock scaler (10 Mbit).
    -- Initial tx clock scaler (10 Mbit).
 
    type impl_to_real_type is array(spw_implementation_type) of real;
 
    constant tximpl_to_txclk_freq: impl_to_real_type :=
 
        (impl_generic => sysfreq, impl_fast => txclkfreq);
 
    constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl);
    constant default_divcnt:    std_logic_vector(7 downto 0) :=
    constant default_divcnt:    std_logic_vector(7 downto 0) :=
        std_logic_vector(to_unsigned(integer(sysfreq / 10.0e6 - 1.0), 8));
        std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8));
 
 
    -- Registers.
    -- Registers.
    type regs_type is record
    type regs_type is record
        -- packet state
        -- packet state
        rxpacket:       std_logic;      -- '1' when receiving a packet
        rxpacket:       std_logic;      -- '1' when receiving a packet

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