URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [syn/] [spwamba_gr-xc3s1500/] [leon3mp.ucf] - Diff between revs 5 and 7

Rev 5	Rev 7
Line 20...	Line 20...

`NET "clkm" TNM_NET = "clkm";`	`NET "clkm" TNM_NET = "clkm";`

`# Timing constraints between 200 MHz SpaceWire clock and system clock.`	`# Timing constraints between 200 MHz SpaceWire clock and system clock.`
`NET "spw_clkl" TNM_NET = "spwclk";`	`NET "spw_clkl" TNM_NET = "spwclk";`
`TIMESPEC "TS_spwclk_to_clkm" = FROM "spwclk" TO "clkm" 3 ns DATAPATHONLY;`	`TIMESPEC "TS_spwclk_to_clkm" = FROM "spwclk" TO "clkm" 4 ns DATAPATHONLY;`
`TIMESPEC "TS_clkm_to_spwclk" = FROM "clkm" TO "spwclk" 3 ns DATAPATHONLY;`	`TIMESPEC "TS_clkm_to_spwclk" = FROM "clkm" TO "spwclk" 4 ns DATAPATHONLY;`
`NET "clkm" MAXSKEW = 1 ns;`	`TIMESPEC "TS_sync" = FROM FFS("/syncdff_ff1") TO FFS("/syncdff_ff2") 2 ns;`
`NET "spw_clkl" MAXSKEW = 1 ns;`

`## Input to DCM for 200 MHz SpaceWire clock can not be optimally routed.`	`## Input to DCM for 200 MHz SpaceWire clock can not be optimally routed.`
`PIN "spwclk0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;`	`PIN "spwclk0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;`

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