OpenCores
URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [syn/] [streamtest_digilent-xc3s200/] [streamtest.ucf] - Diff between revs 2 and 6

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 2 Rev 6
Line 3... Line 3...
# Board clock, 50 MHz = 20 ns nominal, - 2 ns margin = 18 ns
# Board clock, 50 MHz = 20 ns nominal, - 2 ns margin = 18 ns
NET "clk50" TNM_NET = "clk50" ;
NET "clk50" TNM_NET = "clk50" ;
TIMESPEC "TS_clk" = PERIOD "clk50" 18.0 ns ;
TIMESPEC "TS_clk" = PERIOD "clk50" 18.0 ns ;
 
 
# Paths between fastclk and sysclk must be constrained to fastclk period.
# Paths between fastclk and sysclk must be constrained to fastclk period.
# fastclk = 200 MHz = 5 ns nominal, - 1 ns margin = 4 ns
# fastclk = 200 MHz = 5 ns = 3 ns delay + 2 ns skew
NET "sysclk" TNM_NET = "sysclk" ;
NET "sysclk" TNM_NET = "sysclk" | MAXSKEW = 1 ns;
NET "fastclk" TNM_NET = "fastclk" ;
NET "fastclk" TNM_NET = "fastclk" | MAXSKEW = 1 ns;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 3 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 3 ns DATAPATHONLY ;
 
 
NET "clk50"      LOC = "T9" ;
NET "clk50"      LOC = "T9" ;
NET "led(0)"     LOC = "K12" | DRIVE = 6 ;
NET "led(0)"     LOC = "K12" | DRIVE = 6 ;
NET "led(1)"     LOC = "P14" | DRIVE = 6 ;
NET "led(1)"     LOC = "P14" | DRIVE = 6 ;
NET "led(2)"     LOC = "L12" | DRIVE = 6 ;
NET "led(2)"     LOC = "L12" | DRIVE = 6 ;

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.