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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1503605346490 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1516735621447 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1503605346525 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 24 17:09:06 2017 " "Processing started: Thu Aug 24 17:09:06 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1503605346525 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605346525 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Shell Quartus Prime " "Running Quartus Prime Shell" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1516735621464 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 23 17:27:00 2018 " "Processing started: Tue Jan 23 17:27:00 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1516735621464 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605346527 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sh --ip_upgrade -variation_files ulight_fifo.qsys spw_fifo_ulight " "Command: quartus_sh --ip_upgrade -variation_files ulight_fifo.qsys spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1503605356357 ""}
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{ "Info" "IQEXE_START_BANNER_TCL_ARGS" "-variation_files ulight_fifo.qsys spw_fifo_ulight " "Quartus(args): -variation_files ulight_fifo.qsys spw_fifo_ulight" { } { } 0 0 "Quartus(args): %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1503605356357 ""}
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{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "ulight_fifo.qsys ulight_fifo.BAK.qsys " "Backing up file \"ulight_fifo.qsys\" to \"ulight_fifo.BAK.qsys\"" { } { } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653410 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/detector_tokens.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/detector_tokens.v" { { "Info" "ISGN_ENTITY_NAME" "1 detector_tokens " "Found entity 1: detector_tokens" { } { { "../rtl/fpga_debug/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/detector_tokens.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376205 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376205 ""}
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{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "ulight_fifo/synthesis/ulight_fifo.v ulight_fifo.BAK.v " "Backing up file \"ulight_fifo/synthesis/ulight_fifo.v\" to \"ulight_fifo.BAK.v\"" { } { } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653455 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_rx " "Found entity 1: fifo_rx" { } { { "../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_rx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376207 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376207 ""}
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{ "Info" "IIPMAN_IPRGEN_START" "Qsys ulight_fifo.qsys " "Started upgrading IP component Qsys with file \"ulight_fifo.qsys\"" { } { } 0 11837 "Started upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653457 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_tx " "Found entity 1: fifo_tx" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376208 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376208 ""}
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{ "Info" "" "" "2018.01.23.17:28:24 Info: Starting to upgrade the IP cores in the Platform Designer system" { } { } 0 0 "2018.01.23.17:28:24 Info: Starting to upgrade the IP cores in the Platform Designer system" 0 0 "Shell" 0 -1 1516735704060 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fsm_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fsm_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 FSM_SPW " "Found entity 1: FSM_SPW" { } { { "../rtl/RTL_VB/fsm_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fsm_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376209 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376209 ""}
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{ "Info" "" "" "2018.01.23.17:28:24 Info: Finished upgrading the ip cores" { } { } 0 0 "2018.01.23.17:28:24 Info: Finished upgrading the ip cores" 0 0 "Shell" 0 -1 1516735704118 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" { { "Info" "ISGN_ENTITY_NAME" "1 spw_ulight_con_top_x " "Found entity 1: spw_ulight_con_top_x" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376211 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376211 ""}
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{ "Info" "ulight_fifo_generation.rpt" "" "2018.01.23.17:28:59 Info: Saving generation log to /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo" { } { } 0 0 "2018.01.23.17:28:59 Info: Saving generation log to /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo" 0 0 "Shell" 0 -1 1516735739162 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 RX_SPW " "Found entity 1: RX_SPW" { } { { "../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376215 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376215 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Starting: Create simulation model" { } { } 0 0 "2018.01.23.17:28:59 Info: Starting: Create simulation model" 0 0 "Shell" 0 -1 1516735739163 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_spw_ultra_light " "Found entity 1: top_spw_ultra_light" { } { { "../rtl/RTL_VB/top_spw_ultra_light.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376217 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376217 ""}
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{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:28:59 Info: Loading spw_fifo_ulight" { } { } 0 0 "2018.01.23.17:28:59 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735739395 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/tx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/tx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 TX_SPW " "Found entity 1: TX_SPW" { } { { "../rtl/RTL_VB/tx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/tx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376222 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376222 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Reading input file" { } { } 0 0 "2018.01.23.17:28:59 Info: Reading input file" 0 0 "Shell" 0 -1 1516735739472 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/clock_reduce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/clock_reduce.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_reduce " "Found entity 1: clock_reduce" { } { { "../rtl/fpga_debug/clock_reduce.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/clock_reduce.v" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376224 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376224 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding auto_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739501 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/debounce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/debounce.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce_db " "Found entity 1: debounce_db" { } { { "../rtl/fpga_debug/debounce.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/debounce.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376226 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376226 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module auto_start" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735739502 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/ulight_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/ulight_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo " "Found entity 1: ulight_fifo" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376231 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376231 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding clk_0 \[clock_source 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735739503 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376233 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376233 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module clk_0" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735739503 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376235 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376235 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739504 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0 " "Found entity 1: ulight_fifo_mm_interconnect_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376269 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376269 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module clock_sel" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735739505 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376270 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376270 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739506 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376271 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376271 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module counter_rx_fifo" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735739510 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376274 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376274 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739513 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376275 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376275 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376275 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module counter_tx_fifo" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735739515 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376276 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376276 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739516 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376278 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376278 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_flag_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735739520 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376282 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376282 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739522 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter " "Found entity 1: altera_merlin_burst_adapter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376286 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_info" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735739523 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_uncompressed_only " "Found entity 1: altera_merlin_burst_adapter_uncompressed_only" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376287 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376287 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739525 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv 5 5 " "Found 5 design units, including 5 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter_13_1 " "Found entity 5: altera_merlin_burst_adapter_13_1" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376294 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_read_en_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735739527 ""}
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BYTE_TO_WORD_SHIFT byte_to_word_shift altera_merlin_burst_adapter_new.sv(139) " "Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object \"BYTE_TO_WORD_SHIFT\" differs only in case from object \"byte_to_word_shift\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 139 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376302 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739528 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_new " "Found entity 1: altera_merlin_burst_adapter_new" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376303 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376303 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_rx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735739543 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_incr_burst_converter " "Found entity 1: altera_incr_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376306 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739544 ""}
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "addr_incr ADDR_INCR altera_wrap_burst_converter.sv(279) " "Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object \"addr_incr\" differs only in case from object \"ADDR_INCR\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 279 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376308 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_tx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735739544 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_wrap_burst_converter " "Found entity 1: altera_wrap_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376309 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376309 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739546 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_default_burst_converter " "Found entity 1: altera_default_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376311 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376311 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_rx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735739546 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376315 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376315 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739547 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_stage " "Found entity 1: altera_avalon_st_pipeline_stage" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376319 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376319 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_tx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_tx_status" 0 0 "Shell" 0 -1 1516735739548 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376321 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376321 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739548 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376325 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fsm_info" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fsm_info" 0 0 "Shell" 0 -1 1516735739549 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_reorder_memory " "Found entity 1: altera_merlin_reorder_memory" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376328 ""} { "Info" "ISGN_ENTITY_NAME" "2 memory_pointer_controller " "Found entity 2: memory_pointer_controller" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 185 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376328 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376328 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding hps_0 \[altera_hps 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735739550 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376332 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376332 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module hps_0" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735739564 ""}
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router_002.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376334 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739586 ""}
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router_002.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376334 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module led_pio_test" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735739586 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_002_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_002_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376335 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router_002 " "Found entity 2: ulight_fifo_mm_interconnect_0_router_002" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376335 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376335 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding link_disable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739588 ""}
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376336 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module link_disable" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735739589 ""}
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376336 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding link_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739590 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376338 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router " "Found entity 2: ulight_fifo_mm_interconnect_0_router" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376338 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376338 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module link_start" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735739598 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376342 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376342 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding pll_0 \[altera_pll 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735739599 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376345 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376345 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module pll_0" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735739600 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_axi_master_ni " "Found entity 1: altera_merlin_axi_master_ni" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376352 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376352 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739604 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376356 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376356 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_ready_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735739605 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_write_data_fifo_tx " "Found entity 1: ulight_fifo_write_data_fifo_tx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376358 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376358 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739606 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_tx_data " "Found entity 1: ulight_fifo_timecode_tx_data" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376360 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376360 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735739612 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_rx " "Found entity 1: ulight_fifo_timecode_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376362 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376362 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739614 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_pll_0 " "Found entity 1: ulight_fifo_pll_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376364 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376364 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_data" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735739615 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_led_pio_test " "Found entity 1: ulight_fifo_led_pio_test" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376366 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739616 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0 " "Found entity 1: ulight_fifo_hps_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376368 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376368 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_enable" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_enable" 0 0 "Shell" 0 -1 1516735739625 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io " "Found entity 1: ulight_fifo_hps_0_hps_io" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376371 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376371 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739627 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram " "Found entity 1: hps_sdram" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376377 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376377 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_ready" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_ready" 0 0 "Shell" 0 -1 1516735739627 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_pll " "Found entity 1: hps_sdram_pll" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376379 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376379 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739628 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_clock_pair_generator " "Found entity 1: hps_sdram_p0_clock_pair_generator" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376454 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376454 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module write_data_fifo_tx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735739629 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_addr_cmd_pads " "Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376457 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739630 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_memphy " "Found entity 1: hps_sdram_p0_acv_hard_memphy" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376461 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module write_en_tx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735739631 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_ldc " "Found entity 1: hps_sdram_p0_acv_ldc" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376463 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Building connections" { } { } 0 0 "2018.01.23.17:28:59 Info: Building connections" 0 0 "Shell" 0 -1 1516735739632 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_io_pads " "Found entity 1: hps_sdram_p0_acv_hard_io_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376465 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing connections" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing connections" 0 0 "Shell" 0 -1 1516735739642 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_generic_ddio " "Found entity 1: hps_sdram_p0_generic_ddio" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376467 ""}
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{ "Info" "" "" "2018.01.23.17:28:59 Info: Validating" { } { } 0 0 "2018.01.23.17:28:59 Info: Validating" 0 0 "Shell" 0 -1 1516735739645 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset " "Found entity 1: hps_sdram_p0_reset" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376470 ""}
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{ "Info" "" "" "2018.01.23.17:29:08 Info: Done reading input file" { } { } 0 0 "2018.01.23.17:29:08 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735748747 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset_sync " "Found entity 1: hps_sdram_p0_reset_sync" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376474 ""}
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{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752187 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_phy_csr " "Found entity 1: hps_sdram_p0_phy_csr" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376476 ""}
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{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752187 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_iss_probe " "Found entity 1: hps_sdram_p0_iss_probe" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376478 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376478 ""}
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{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735752190 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0 " "Found entity 1: hps_sdram_p0" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376481 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376481 ""}
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{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735752190 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_altdqdqs " "Found entity 1: hps_sdram_p0_altdqdqs" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376483 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376483 ""}
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{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735752196 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altdq_dqs2_acv_connect_to_hard_phy_cyclonev " "Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376493 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376493 ""}
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{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" { } { } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735752197 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hhp_qseq_synth_top " "Found entity 1: altera_mem_if_hhp_qseq_synth_top" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376495 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376495 ""}
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{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" { } { } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735752198 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hard_memory_controller_top_cyclonev " "Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376508 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376508 ""}
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{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735752198 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_oct_cyclonev " "Found entity 1: altera_mem_if_oct_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376510 ""}
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{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" { } { } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735752198 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_dll_cyclonev " "Found entity 1: altera_mem_if_dll_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376511 ""}
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{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752199 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io_border " "Found entity 1: ulight_fifo_hps_0_hps_io_border" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376513 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376513 ""}
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{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752199 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_fpga_interfaces " "Found entity 1: ulight_fifo_hps_0_fpga_interfaces" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376515 ""}
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{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752200 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_fifo_empty_rx_status " "Found entity 1: ulight_fifo_fifo_empty_rx_status" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376517 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376517 ""}
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{ "Info" "" "" "2018.01.23.17:29:16 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for SIM_VERILOG" { } { } 0 0 "2018.01.23.17:29:16 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for SIM_VERILOG" 0 0 "Shell" 0 -1 1516735756855 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_info " "Found entity 1: ulight_fifo_data_info" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376519 ""}
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{ "Warning" "" "" "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" { } { } 0 0 "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" 0 0 "Shell" 0 -1 1516735775279 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_flag_rx " "Found entity 1: ulight_fifo_data_flag_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376521 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376521 ""}
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{ "Warning" "" "" "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" { } { } 0 0 "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" 0 0 "Shell" 0 -1 1516735775279 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_counter_rx_fifo " "Found entity 1: ulight_fifo_counter_rx_fifo" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376523 ""}
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{ "Info" "" "" "2018.01.23.17:29:39 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:29:39 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735779023 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_clock_sel " "Found entity 1: ulight_fifo_clock_sel" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376525 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376525 ""}
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{ "Info" " ]" "" "2018.01.23.17:29:39 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen" { } { } 0 0 "2018.01.23.17:29:39 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen" 0 0 "Shell" 0 -1 1516735779023 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_auto_start " "Found entity 1: ulight_fifo_auto_start" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376527 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376527 ""}
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{ "Info" "" "" "2018.01.23.17:29:40 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:29:40 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735780647 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_rtl/spw_fifo_ulight.v 1 1 " "Found 1 design units, including 1 entities, in source file top_rtl/spw_fifo_ulight.v" { { "Info" "ISGN_ENTITY_NAME" "1 SPW_ULIGHT_FIFO " "Found entity 1: SPW_ULIGHT_FIFO" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376530 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376530 ""}
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{ "Info" "" "" "2018.01.23.17:29:40 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" { } { } 0 0 "2018.01.23.17:29:40 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" 0 0 "Shell" 0 -1 1516735780650 ""}
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{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "top_tx_ready_tick spw_fifo_ulight.v(96) " "Verilog HDL Implicit Net warning at spw_fifo_ulight.v(96): created implicit net for \"top_tx_ready_tick\"" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 96 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376532 ""}
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{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735780733 ""}
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{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for \"pll_dr_clk\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376533 ""}
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{ "Info" " ]" "" "2018.01.23.17:29:40 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen" 0 0 "Shell" 0 -1 1516735780733 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "SPW_ULIGHT_FIFO " "Elaborating entity \"SPW_ULIGHT_FIFO\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1503605376809 ""}
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{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735780886 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[6\] spw_fifo_ulight.v(17) " "Output port \"LED\[6\]\" at spw_fifo_ulight.v(17) has no driver" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376811 "|SPW_ULIGHT_FIFO"}
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{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" 0 0 "Shell" 0 -1 1516735780888 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo ulight_fifo:u0 " "Elaborating entity \"ulight_fifo\" for hierarchy \"ulight_fifo:u0\"" { } { { "top_rtl/spw_fifo_ulight.v" "u0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376816 ""}
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{ "Info" "" "" "2018.01.23.17:29:40 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" { } { } 0 0 "2018.01.23.17:29:40 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735780972 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_auto_start ulight_fifo:u0\|ulight_fifo_auto_start:auto_start " "Elaborating entity \"ulight_fifo_auto_start\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_auto_start:auto_start\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "auto_start" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 174 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376829 ""}
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{ "Info" " ]" "" "2018.01.23.17:29:40 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen" { } { } 0 0 "2018.01.23.17:29:40 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen" 0 0 "Shell" 0 -1 1516735780972 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_clock_sel ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel " "Elaborating entity \"ulight_fifo_clock_sel\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "clock_sel" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 185 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376834 ""}
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{ "Info" "" "" "2018.01.23.17:29:41 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'\n2018.01.23.17:29:41 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" { } { } 0 0 "2018.01.23.17:29:41 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'\n2018.01.23.17:29:41 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" 0 0 "Shell" 0 -1 1516735781099 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_counter_rx_fifo ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo " "Elaborating entity \"ulight_fifo_counter_rx_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "counter_rx_fifo" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376838 ""}
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{ "Info" "" "" "2018.01.23.17:29:41 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" { } { } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735781242 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_flag_rx ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx " "Elaborating entity \"ulight_fifo_data_flag_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_flag_rx" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 209 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376843 ""}
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{ "Info" " ]" "" "2018.01.23.17:29:41 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen" { } { } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen" 0 0 "Shell" 0 -1 1516735781242 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_info ulight_fifo:u0\|ulight_fifo_data_info:data_info " "Elaborating entity \"ulight_fifo_data_info\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_info:data_info\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_info" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 217 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376847 ""}
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{ "Info" "" "" "2018.01.23.17:29:41 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'\n2018.01.23.17:29:41 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" { } { } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'\n2018.01.23.17:29:41 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" 0 0 "Shell" 0 -1 1516735781379 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_fifo_empty_rx_status ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status " "Elaborating entity \"ulight_fifo_fifo_empty_rx_status\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "fifo_empty_rx_status" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 236 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376853 ""}
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{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735781502 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0 " "Elaborating entity \"ulight_fifo_hps_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "hps_0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376880 ""}
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{ "Info" " ]" "" "2018.01.23.17:29:41 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen" 0 0 "Shell" 0 -1 1516735781502 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_fpga_interfaces ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces " "Elaborating entity \"ulight_fifo_hps_0_fpga_interfaces\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "fpga_interfaces" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376896 ""}
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{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735781634 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io " "Elaborating entity \"ulight_fifo_hps_0_hps_io\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "hps_io" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376914 ""}
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{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" 0 0 "Shell" 0 -1 1516735781635 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io_border ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border " "Elaborating entity \"ulight_fifo_hps_0_hps_io_border\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "border" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 45 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376927 ""}
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{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735781751 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst " "Elaborating entity \"hps_sdram\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "hps_sdram_inst" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 84 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376937 ""}
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{ "Info" " ]" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen" 0 0 "Shell" 0 -1 1516735781752 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_pll ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll " "Elaborating entity \"hps_sdram_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "pll" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376944 ""}
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{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735781904 ""}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object \"pll_dr_clk\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503605376945 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"}
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{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" 0 0 "Shell" 0 -1 1516735781906 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "pll_locked hps_sdram_pll.sv(91) " "Output port \"pll_locked\" at hps_sdram_pll.sv(91) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 91 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376945 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"}
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{ "Info" "" "" "2018.01.23.17:29:41 Info: hps_0: \"Running for module: hps_0\"" { } { } 0 0 "2018.01.23.17:29:41 Info: hps_0: \"Running for module: hps_0\"" 0 0 "Shell" 0 -1 1516735781908 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0 " "Elaborating entity \"hps_sdram_p0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "p0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 230 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376950 ""}
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{ "Info" "" "" "2018.01.23.17:29:42 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:29:42 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735782735 ""}
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{ "Info" "IVRFX_VERI_DISPLAY_SYSTEM_CALL_INFO" "Using Regular core emif simulation models hps_sdram_p0.sv(405) " "Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 405 0 0 } } } 0 10648 "Verilog HDL Display System Task info at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376960 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0"}
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{ "Info" "" "" "2018.01.23.17:29:43 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:29:43 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735783333 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_memphy ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy " "Elaborating entity \"hps_sdram_p0_acv_hard_memphy\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "umemphy" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 573 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376962 ""}
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{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:29:43 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735783343 ""}
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{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "reset_n_seq_clk hps_sdram_p0_acv_hard_memphy.v(420) " "Verilog HDL warning at hps_sdram_p0_acv_hard_memphy.v(420): object reset_n_seq_clk used but never assigned" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
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{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:29:43 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735783636 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 hps_sdram_p0_acv_hard_memphy.v(557) " "Verilog HDL assignment warning at hps_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 557 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
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{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:29:43 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735783757 ""}
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "reset_n_seq_clk 0 hps_sdram_p0_acv_hard_memphy.v(420) " "Net \"reset_n_seq_clk\" at hps_sdram_p0_acv_hard_memphy.v(420) has no driver or initial value, using a default initial value '0'" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
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{ "Info" "" "" "2018.01.23.17:29:44 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" { } { } 0 0 "2018.01.23.17:29:44 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" 0 0 "Shell" 0 -1 1516735784424 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ctl_reset_export_n hps_sdram_p0_acv_hard_memphy.v(222) " "Output port \"ctl_reset_export_n\" at hps_sdram_p0_acv_hard_memphy.v(222) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 222 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
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{ "Info" " ]" "" "2018.01.23.17:29:44 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen" { } { } 0 0 "2018.01.23.17:29:44 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen" 0 0 "Shell" 0 -1 1516735784521 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_ldc ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc " "Elaborating entity \"hps_sdram_p0_acv_ldc\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "memphy_ldc" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 554 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376971 ""}
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{ "Info" "" "" "2018.01.23.17:29:44 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" { } { } 0 0 "2018.01.23.17:29:44 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" 0 0 "Shell" 0 -1 1516735784720 ""}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dq hps_sdram_p0_acv_ldc.v(45) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(45): object \"phy_clk_dq\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 45 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503605376974 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"}
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{ "Info" "" "" "2018.01.23.17:29:44 Info: pll_0: Generating simgen model" { } { } 0 0 "2018.01.23.17:29:44 Info: pll_0: Generating simgen model" 0 0 "Shell" 0 -1 1516735784779 ""}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dqs_2x hps_sdram_p0_acv_ldc.v(47) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(47): object \"phy_clk_dqs_2x\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503605376974 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"}
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{ "Info" "" "" "2018.01.23.17:30:12 Info: pll_0: Simgen was successful" { } { } 0 0 "2018.01.23.17:30:12 Info: pll_0: Simgen was successful" 0 0 "Shell" 0 -1 1516735812813 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_io_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_io_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "uio_pads" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 780 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376978 ""}
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{ "Info" "" "" "2018.01.23.17:30:12 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" { } { } 0 0 "2018.01.23.17:30:12 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" 0 0 "Shell" 0 -1 1516735812815 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ddio_phy_dqdin\[179..32\] hps_sdram_p0_acv_hard_io_pads.v(191) " "Output port \"ddio_phy_dqdin\[179..32\]\" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 191 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376982 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads"}
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{ "Info" "" "" "2018.01.23.17:30:12 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:30:12 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735812969 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_addr_cmd_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_addr_cmd_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "uaddr_cmd_pads" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 244 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376985 ""}
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{ "Info" " ]" "" "2018.01.23.17:30:12 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen" { } { } 0 0 "2018.01.23.17:30:12 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen" 0 0 "Shell" 0 -1 1516735812970 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "uaddress_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377094 ""}
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{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735813142 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ubank_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 166 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377115 ""}
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{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" 0 0 "Shell" 0 -1 1516735813144 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ucmd_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377125 ""}
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{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735813212 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ureset_n_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 198 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377142 ""}
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{ "Info" " ]" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen" 0 0 "Shell" 0 -1 1516735813212 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborating entity \"altddio_out\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].umem_ck_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377201 ""}
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{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735813329 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377202 ""}
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{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" 0 0 "Shell" 0 -1 1516735813330 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "extend_oe_disable UNUSED " "Parameter \"extend_oe_disable\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "invert_output OFF " "Parameter \"invert_output\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altddio_out " "Parameter \"lpm_type\" = \"altddio_out\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "oe_reg UNUSED " "Parameter \"oe_reg\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_high OFF " "Parameter \"power_up_high\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 1 " "Parameter \"width\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1503605377203 ""}
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{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735813400 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ddio_out_uqe.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ddio_out_uqe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ddio_out_uqe " "Found entity 1: ddio_out_uqe" { } { { "db/ddio_out_uqe.tdf" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/db/ddio_out_uqe.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605377273 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605377273 ""}
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{ "Info" " ]" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen" 0 0 "Shell" 0 -1 1516735813401 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddio_out_uqe ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated " "Elaborating entity \"ddio_out_uqe\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated\"" { } { { "altddio_out.tdf" "auto_generated" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altddio_out.tdf" 101 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377274 ""}
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{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735813531 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_clock_pair_generator ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator " "Elaborating entity \"hps_sdram_p0_clock_pair_generator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].uclk_generator" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 337 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377284 ""}
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{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" 0 0 "Shell" 0 -1 1516735813533 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_altdqdqs ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs " "Elaborating entity \"hps_sdram_p0_altdqdqs\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "dq_ddio\[0\].ubidir_dq_dqs" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377290 ""}
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{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815764 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdq_dqs2_acv_connect_to_hard_phy_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst " "Elaborating entity \"altdq_dqs2_acv_connect_to_hard_phy_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "altdq_dqs2_inst" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 146 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377294 ""}
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{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815843 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hhp_qseq_synth_top ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq " "Elaborating entity \"altera_mem_if_hhp_qseq_synth_top\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "seq" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 238 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377365 ""}
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{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815918 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hard_memory_controller_top_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0 " "Elaborating entity \"altera_mem_if_hard_memory_controller_top_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "c0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377372 ""}
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{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815973 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1166 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377380 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816040 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377381 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816108 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377381 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816205 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377381 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816278 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377381 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816352 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377382 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816421 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_oct_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct " "Elaborating entity \"altera_mem_if_oct_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "oct" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377388 ""}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816501 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_dll_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll " "Elaborating entity \"altera_mem_if_dll_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "dll" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 814 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377392 ""}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816574 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_led_pio_test ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test " "Elaborating entity \"ulight_fifo_led_pio_test\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "led_pio_test" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 339 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377397 ""}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816654 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_pll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0 " "Elaborating entity \"ulight_fifo_pll_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "pll_0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377407 ""}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816731 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborating entity \"altera_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "altera_pll_i" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377454 ""}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816801 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvds_clk altera_pll.v(320) " "Output port \"lvds_clk\" at altera_pll.v(320) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 320 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377458 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816868 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_pll.v(321) " "Output port \"loaden\" at altera_pll.v(321) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 321 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377458 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"}
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{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816942 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk_out altera_pll.v(322) " "Output port \"extclk_out\" at altera_pll.v(322) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 322 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377458 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"}
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{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817025 ""}
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{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "wire_to_nowhere_64 " "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"wire_to_nowhere_64\" into its bus" { } { } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "Analysis & Synthesis" 0 -1 1503605377458 ""}
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{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817110 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377458 ""}
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{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817182 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "fractional_vco_multiplier false " "Parameter \"fractional_vco_multiplier\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "reference_clock_frequency 100.0 MHz " "Parameter \"reference_clock_frequency\" = \"100.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_cout 32 " "Parameter \"pll_fractional_cout\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_dsm_out_sel 1st_order " "Parameter \"pll_dsm_out_sel\" = \"1st_order\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode direct " "Parameter \"operation_mode\" = \"direct\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_clocks 1 " "Parameter \"number_of_clocks\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency0 400.000000 MHz " "Parameter \"output_clock_frequency0\" = \"400.000000 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift0 0 ps " "Parameter \"phase_shift0\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle0 50 " "Parameter \"duty_cycle0\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency1 0 MHz " "Parameter \"output_clock_frequency1\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift1 0 ps " "Parameter \"phase_shift1\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle1 50 " "Parameter \"duty_cycle1\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency2 0 MHz " "Parameter \"output_clock_frequency2\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift2 0 ps " "Parameter \"phase_shift2\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle2 50 " "Parameter \"duty_cycle2\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency3 0 MHz " "Parameter \"output_clock_frequency3\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift3 0 ps " "Parameter \"phase_shift3\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle3 50 " "Parameter \"duty_cycle3\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency4 0 MHz " "Parameter \"output_clock_frequency4\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift4 0 ps " "Parameter \"phase_shift4\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle4 50 " "Parameter \"duty_cycle4\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency5 0 MHz " "Parameter \"output_clock_frequency5\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift5 0 ps " "Parameter \"phase_shift5\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle5 50 " "Parameter \"duty_cycle5\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency6 0 MHz " "Parameter \"output_clock_frequency6\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift6 0 ps " "Parameter \"phase_shift6\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle6 50 " "Parameter \"duty_cycle6\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency7 0 MHz " "Parameter \"output_clock_frequency7\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift7 0 ps " "Parameter \"phase_shift7\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle7 50 " "Parameter \"duty_cycle7\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency8 0 MHz " "Parameter \"output_clock_frequency8\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift8 0 ps " "Parameter \"phase_shift8\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle8 50 " "Parameter \"duty_cycle8\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency9 0 MHz " "Parameter \"output_clock_frequency9\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift9 0 ps " "Parameter \"phase_shift9\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle9 50 " "Parameter \"duty_cycle9\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency10 0 MHz " "Parameter \"output_clock_frequency10\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift10 0 ps " "Parameter \"phase_shift10\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle10 50 " "Parameter \"duty_cycle10\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency11 0 MHz " "Parameter \"output_clock_frequency11\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift11 0 ps " "Parameter \"phase_shift11\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle11 50 " "Parameter \"duty_cycle11\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency12 0 MHz " "Parameter \"output_clock_frequency12\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift12 0 ps " "Parameter \"phase_shift12\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle12 50 " "Parameter \"duty_cycle12\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency13 0 MHz " "Parameter \"output_clock_frequency13\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift13 0 ps " "Parameter \"phase_shift13\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle13 50 " "Parameter \"duty_cycle13\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency14 0 MHz " "Parameter \"output_clock_frequency14\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift14 0 ps " "Parameter \"phase_shift14\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle14 50 " "Parameter \"duty_cycle14\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency15 0 MHz " "Parameter \"output_clock_frequency15\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift15 0 ps " "Parameter \"phase_shift15\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle15 50 " "Parameter \"duty_cycle15\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency16 0 MHz " "Parameter \"output_clock_frequency16\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift16 0 ps " "Parameter \"phase_shift16\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle16 50 " "Parameter \"duty_cycle16\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency17 0 MHz " "Parameter \"output_clock_frequency17\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift17 0 ps " "Parameter \"phase_shift17\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle17 50 " "Parameter \"duty_cycle17\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type Cyclone V " "Parameter \"pll_type\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_subtype General " "Parameter \"pll_subtype\" = \"General\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_hi_div 2 " "Parameter \"m_cnt_hi_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_lo_div 2 " "Parameter \"m_cnt_lo_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_hi_div 256 " "Parameter \"n_cnt_hi_div\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_lo_div 256 " "Parameter \"n_cnt_lo_div\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_bypass_en false " "Parameter \"m_cnt_bypass_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_bypass_en true " "Parameter \"n_cnt_bypass_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_odd_div_duty_en false " "Parameter \"m_cnt_odd_div_duty_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_odd_div_duty_en false " "Parameter \"n_cnt_odd_div_duty_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div0 256 " "Parameter \"c_cnt_hi_div0\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div0 256 " "Parameter \"c_cnt_lo_div0\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst0 1 " "Parameter \"c_cnt_prst0\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst0 0 " "Parameter \"c_cnt_ph_mux_prst0\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src0 ph_mux_clk " "Parameter \"c_cnt_in_src0\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en0 true " "Parameter \"c_cnt_bypass_en0\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en0 false " "Parameter \"c_cnt_odd_div_duty_en0\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div1 1 " "Parameter \"c_cnt_hi_div1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div1 1 " "Parameter \"c_cnt_lo_div1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst1 1 " "Parameter \"c_cnt_prst1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst1 0 " "Parameter \"c_cnt_ph_mux_prst1\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src1 ph_mux_clk " "Parameter \"c_cnt_in_src1\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en1 true " "Parameter \"c_cnt_bypass_en1\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en1 false " "Parameter \"c_cnt_odd_div_duty_en1\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div2 1 " "Parameter \"c_cnt_hi_div2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div2 1 " "Parameter \"c_cnt_lo_div2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst2 1 " "Parameter \"c_cnt_prst2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst2 0 " "Parameter \"c_cnt_ph_mux_prst2\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src2 ph_mux_clk " "Parameter \"c_cnt_in_src2\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en2 true " "Parameter \"c_cnt_bypass_en2\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en2 false " "Parameter \"c_cnt_odd_div_duty_en2\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div3 1 " "Parameter \"c_cnt_hi_div3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div3 1 " "Parameter \"c_cnt_lo_div3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst3 1 " "Parameter \"c_cnt_prst3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst3 0 " "Parameter \"c_cnt_ph_mux_prst3\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src3 ph_mux_clk " "Parameter \"c_cnt_in_src3\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en3 true " "Parameter \"c_cnt_bypass_en3\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en3 false " "Parameter \"c_cnt_odd_div_duty_en3\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div4 1 " "Parameter \"c_cnt_hi_div4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div4 1 " "Parameter \"c_cnt_lo_div4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst4 1 " "Parameter \"c_cnt_prst4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst4 0 " "Parameter \"c_cnt_ph_mux_prst4\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src4 ph_mux_clk " "Parameter \"c_cnt_in_src4\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en4 true " "Parameter \"c_cnt_bypass_en4\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en4 false " "Parameter \"c_cnt_odd_div_duty_en4\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div5 1 " "Parameter \"c_cnt_hi_div5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div5 1 " "Parameter \"c_cnt_lo_div5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst5 1 " "Parameter \"c_cnt_prst5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst5 0 " "Parameter \"c_cnt_ph_mux_prst5\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src5 ph_mux_clk " "Parameter \"c_cnt_in_src5\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en5 true " "Parameter \"c_cnt_bypass_en5\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en5 false " "Parameter \"c_cnt_odd_div_duty_en5\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div6 1 " "Parameter \"c_cnt_hi_div6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div6 1 " "Parameter \"c_cnt_lo_div6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst6 1 " "Parameter \"c_cnt_prst6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst6 0 " "Parameter \"c_cnt_ph_mux_prst6\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src6 ph_mux_clk " "Parameter \"c_cnt_in_src6\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en6 true " "Parameter \"c_cnt_bypass_en6\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en6 false " "Parameter \"c_cnt_odd_div_duty_en6\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div7 1 " "Parameter \"c_cnt_hi_div7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div7 1 " "Parameter \"c_cnt_lo_div7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst7 1 " "Parameter \"c_cnt_prst7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst7 0 " "Parameter \"c_cnt_ph_mux_prst7\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src7 ph_mux_clk " "Parameter \"c_cnt_in_src7\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en7 true " "Parameter \"c_cnt_bypass_en7\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en7 false " "Parameter \"c_cnt_odd_div_duty_en7\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div8 1 " "Parameter \"c_cnt_hi_div8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div8 1 " "Parameter \"c_cnt_lo_div8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst8 1 " "Parameter \"c_cnt_prst8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst8 0 " "Parameter \"c_cnt_ph_mux_prst8\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src8 ph_mux_clk " "Parameter \"c_cnt_in_src8\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en8 true " "Parameter \"c_cnt_bypass_en8\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en8 false " "Parameter \"c_cnt_odd_div_duty_en8\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div9 1 " "Parameter \"c_cnt_hi_div9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div9 1 " "Parameter \"c_cnt_lo_div9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst9 1 " "Parameter \"c_cnt_prst9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst9 0 " "Parameter \"c_cnt_ph_mux_prst9\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src9 ph_mux_clk " "Parameter \"c_cnt_in_src9\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en9 true " "Parameter \"c_cnt_bypass_en9\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en9 false " "Parameter \"c_cnt_odd_div_duty_en9\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div10 1 " "Parameter \"c_cnt_hi_div10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div10 1 " "Parameter \"c_cnt_lo_div10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst10 1 " "Parameter \"c_cnt_prst10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst10 0 " "Parameter \"c_cnt_ph_mux_prst10\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src10 ph_mux_clk " "Parameter \"c_cnt_in_src10\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en10 true " "Parameter \"c_cnt_bypass_en10\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en10 false " "Parameter \"c_cnt_odd_div_duty_en10\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div11 1 " "Parameter \"c_cnt_hi_div11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div11 1 " "Parameter \"c_cnt_lo_div11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst11 1 " "Parameter \"c_cnt_prst11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst11 0 " "Parameter \"c_cnt_ph_mux_prst11\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src11 ph_mux_clk " "Parameter \"c_cnt_in_src11\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en11 true " "Parameter \"c_cnt_bypass_en11\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en11 false " "Parameter \"c_cnt_odd_div_duty_en11\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div12 1 " "Parameter \"c_cnt_hi_div12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div12 1 " "Parameter \"c_cnt_lo_div12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst12 1 " "Parameter \"c_cnt_prst12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst12 0 " "Parameter \"c_cnt_ph_mux_prst12\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src12 ph_mux_clk " "Parameter \"c_cnt_in_src12\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en12 true " "Parameter \"c_cnt_bypass_en12\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en12 false " "Parameter \"c_cnt_odd_div_duty_en12\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div13 1 " "Parameter \"c_cnt_hi_div13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div13 1 " "Parameter \"c_cnt_lo_div13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst13 1 " "Parameter \"c_cnt_prst13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst13 0 " "Parameter \"c_cnt_ph_mux_prst13\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src13 ph_mux_clk " "Parameter \"c_cnt_in_src13\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en13 true " "Parameter \"c_cnt_bypass_en13\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en13 false " "Parameter \"c_cnt_odd_div_duty_en13\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div14 1 " "Parameter \"c_cnt_hi_div14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div14 1 " "Parameter \"c_cnt_lo_div14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst14 1 " "Parameter \"c_cnt_prst14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst14 0 " "Parameter \"c_cnt_ph_mux_prst14\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src14 ph_mux_clk " "Parameter \"c_cnt_in_src14\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en14 true " "Parameter \"c_cnt_bypass_en14\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en14 false " "Parameter \"c_cnt_odd_div_duty_en14\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div15 1 " "Parameter \"c_cnt_hi_div15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div15 1 " "Parameter \"c_cnt_lo_div15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst15 1 " "Parameter \"c_cnt_prst15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst15 0 " "Parameter \"c_cnt_ph_mux_prst15\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src15 ph_mux_clk " "Parameter \"c_cnt_in_src15\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en15 true " "Parameter \"c_cnt_bypass_en15\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en15 false " "Parameter \"c_cnt_odd_div_duty_en15\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div16 1 " "Parameter \"c_cnt_hi_div16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div16 1 " "Parameter \"c_cnt_lo_div16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst16 1 " "Parameter \"c_cnt_prst16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst16 0 " "Parameter \"c_cnt_ph_mux_prst16\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src16 ph_mux_clk " "Parameter \"c_cnt_in_src16\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en16 true " "Parameter \"c_cnt_bypass_en16\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en16 false " "Parameter \"c_cnt_odd_div_duty_en16\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div17 1 " "Parameter \"c_cnt_hi_div17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div17 1 " "Parameter \"c_cnt_lo_div17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst17 1 " "Parameter \"c_cnt_prst17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst17 0 " "Parameter \"c_cnt_ph_mux_prst17\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src17 ph_mux_clk " "Parameter \"c_cnt_in_src17\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en17 true " "Parameter \"c_cnt_bypass_en17\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en17 false " "Parameter \"c_cnt_odd_div_duty_en17\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_vco_div 2 " "Parameter \"pll_vco_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_cp_current 30 " "Parameter \"pll_cp_current\" = \"30\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_bwctrl 2000 " "Parameter \"pll_bwctrl\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_output_clk_frequency 400.0 MHz " "Parameter \"pll_output_clk_frequency\" = \"400.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_division 1 " "Parameter \"pll_fractional_division\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "mimic_fbclk_type none " "Parameter \"mimic_fbclk_type\" = \"none\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_1 glb " "Parameter \"pll_fbclk_mux_1\" = \"glb\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_2 m_cnt " "Parameter \"pll_fbclk_mux_2\" = \"m_cnt\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_m_cnt_in_src ph_mux_clk " "Parameter \"pll_m_cnt_in_src\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_slf_rst false " "Parameter \"pll_slf_rst\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "refclk1_frequency 100.0 MHz " "Parameter \"refclk1_frequency\" = \"100.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_loss_sw_en true " "Parameter \"pll_clk_loss_sw_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_manu_clk_sw_en false " "Parameter \"pll_manu_clk_sw_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_auto_clk_sw_en true " "Parameter \"pll_auto_clk_sw_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clkin_1_src clk_1 " "Parameter \"pll_clkin_1_src\" = \"clk_1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_sw_dly 0 " "Parameter \"pll_clk_sw_dly\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1503605377460 ""}
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{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817249 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dps_extra_kick ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst " "Elaborating entity \"dps_extra_kick\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\"" { } { { "altera_pll.v" "dps_extra_inst" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 769 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377471 ""}
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{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817317 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 769 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377473 ""}
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{ "Info" "" "" "2018.01.23.17:30:20 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" { } { } 0 0 "2018.01.23.17:30:20 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" 0 0 "Shell" 0 -1 1516735820323 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dprio_init ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst " "Elaborating entity \"dprio_init\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\"" { } { { "altera_pll.v" "dprio_init_inst" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 784 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377476 ""}
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{ "Info" "" "" "2018.01.23.17:30:20 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 0 "2018.01.23.17:30:20 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" 0 0 "Shell" 0 -1 1516735820407 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 784 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377477 ""}
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{ "Info" "" "" "2018.01.23.17:30:20 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" { } { } 0 0 "2018.01.23.17:30:20 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" 0 0 "Shell" 0 -1 1516735820733 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\"" { } { { "altera_pll.v" "lcell_cntsel_int_0" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1961 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377486 ""}
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{ "Info" "" "" "2018.01.23.17:30:20 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" { } { } 0 0 "2018.01.23.17:30:20 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" 0 0 "Shell" 0 -1 1516735820852 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1961 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377488 ""}
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{ "Info" "" "" "2018.01.23.17:30:20 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" { } { } 0 0 "2018.01.23.17:30:20 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" 0 0 "Shell" 0 -1 1516735820878 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\"" { } { { "altera_pll.v" "lcell_cntsel_int_1" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1972 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377493 ""}
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{ "Info" "" "" "2018.01.23.17:30:20 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" { } { } 0 0 "2018.01.23.17:30:20 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" 0 0 "Shell" 0 -1 1516735820907 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1972 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377494 ""}
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{ "Info" "" "" "2018.01.23.17:30:20 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" { } { } 0 0 "2018.01.23.17:30:20 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" 0 0 "Shell" 0 -1 1516735820943 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\"" { } { { "altera_pll.v" "lcell_cntsel_int_2" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1983 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377496 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" { } { } 0 0 "2018.01.23.17:30:21 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" 0 0 "Shell" 0 -1 1516735821010 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1983 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377497 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" { } { } 0 0 "2018.01.23.17:30:21 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" 0 0 "Shell" 0 -1 1516735821047 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\"" { } { { "altera_pll.v" "lcell_cntsel_int_3" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1994 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377499 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" { } { } 0 0 "2018.01.23.17:30:21 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" 0 0 "Shell" 0 -1 1516735821058 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1994 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377500 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" { } { } 0 0 "2018.01.23.17:30:21 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" 0 0 "Shell" 0 -1 1516735821132 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\"" { } { { "altera_pll.v" "lcell_cntsel_int_4" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2005 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377503 ""}
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{ "Info" "altera_avalon_sc_fifo.v" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821135 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2005 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377504 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" { } { } 0 0 "2018.01.23.17:30:21 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" 0 0 "Shell" 0 -1 1516735821258 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll " "Elaborating entity \"altera_cyclonev_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\"" { } { { "altera_pll.v" "cyclonev_pll" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2224 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377524 ""}
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{ "Info" "altera_merlin_address_alignment.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821262 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk altera_cyclonev_pll.v(632) " "Output port \"extclk\" at altera_cyclonev_pll.v(632) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 632 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377531 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
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{ "Info" "altera_avalon_st_pipeline_base.v" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821263 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "clkout\[0\] altera_cyclonev_pll.v(637) " "Output port \"clkout\[0\]\" at altera_cyclonev_pll.v(637) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 637 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377532 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" 0 0 "Shell" 0 -1 1516735821319 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_cyclonev_pll.v(641) " "Output port \"loaden\" at altera_cyclonev_pll.v(641) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 641 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377532 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" 0 0 "Shell" 0 -1 1516735821334 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvdsclk altera_cyclonev_pll.v(642) " "Output port \"lvdsclk\" at altera_cyclonev_pll.v(642) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 642 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377532 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" 0 0 "Shell" 0 -1 1516735821340 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2224 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377532 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" 0 0 "Shell" 0 -1 1516735821360 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll_base ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 " "Elaborating entity \"altera_cyclonev_pll_base\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\"" { } { { "altera_cyclonev_pll.v" "fpll_0" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377537 ""}
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{ "Info" "altera_merlin_arbitrator.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821362 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1153 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377542 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" { } { } 0 0 "2018.01.23.17:30:21 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" 0 0 "Shell" 0 -1 1516735821401 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_rx ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx " "Elaborating entity \"ulight_fifo_timecode_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_rx" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 385 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377548 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" { } { } 0 0 "2018.01.23.17:30:21 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" 0 0 "Shell" 0 -1 1516735821470 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_tx_data ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data " "Elaborating entity \"ulight_fifo_timecode_tx_data\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_tx_data" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 396 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377551 ""}
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{ "Info" "verbosity_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821471 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_write_data_fifo_tx ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx " "Elaborating entity \"ulight_fifo_write_data_fifo_tx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "write_data_fifo_tx" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 426 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377560 ""}
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{ "Info" "avalon_utilities_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821471 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "mm_interconnect_0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377564 ""}
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{ "Info" "avalon_mm_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821472 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_translator" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 1962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377760 ""}
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{ "Info" "altera_avalon_mm_slave_bfm.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821474 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_axi_master_ni ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent " "Elaborating entity \"altera_merlin_axi_master_ni\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_agent" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3434 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377814 ""}
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{ "Info" "altera_avalon_interrupt_sink.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821475 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 485 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377819 ""}
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{ "Info" "altera_avalon_clock_source.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821475 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3518 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377824 ""}
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{ "Info" "altera_avalon_reset_source.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821476 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 608 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377828 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" { } { } 0 0 "2018.01.23.17:30:21 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" 0 0 "Shell" 0 -1 1516735821510 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rsp_fifo" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3559 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377833 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 58 files" { } { } 0 0 "2018.01.23.17:30:21 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 58 files" 0 0 "Shell" 0 -1 1516735821511 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rdata_fifo" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3600 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377839 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: qsys-generate succeeded." { } { } 0 0 "2018.01.23.17:30:21 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735821581 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378122 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: Finished: Create simulation model" { } { } 0 0 "2018.01.23.17:30:21 Info: Finished: Create simulation model" 0 0 "Shell" 0 -1 1516735821581 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378129 ""}
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{ "Info" "" "" "2018.01.23.17:30:21 Info: Starting: Create Modelsim Project." { } { } 0 0 "2018.01.23.17:30:21 Info: Starting: Create Modelsim Project." 0 0 "Shell" 0 -1 1516735821582 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router_002" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378140 ""}
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{ "Info" " --use-relative-paths=true" "" "2018.01.23.17:30:21 Info: sim-script-gen --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:21 Info: sim-script-gen --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735821583 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378144 ""}
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{ "Info" " --use-relative-paths=true" "" "2018.01.23.17:30:21 Info: Doing: ip-make-simscript --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:21 Info: Doing: ip-make-simscript --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735821590 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_wr_limiter" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7520 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378244 ""}
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{ "Info" " directory:" "" "2018.01.23.17:30:22 Info: Generating the following file(s) for MODELSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:22 Info: Generating the following file(s) for MODELSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735822982 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7620 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378254 ""}
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{ "Info" "msim_setup.tcl" "" "2018.01.23.17:30:22 Info: mentor" { } { } 0 0 "2018.01.23.17:30:22 Info: mentor" 0 0 "Shell" 0 -1 1516735822983 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_13_1 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter_13_1\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_13_1.burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378259 ""}
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{ "Info" " directory:" "" "2018.01.23.17:30:22 Info: Generating the following file(s) for VCS simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:22 Info: Generating the following file(s) for VCS simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735822995 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 778 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378271 ""}
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{ "Info" "vcs_setup.sh" "" "2018.01.23.17:30:22 Info: synopsys/vcs" { } { } 0 0 "2018.01.23.17:30:22 Info: synopsys/vcs" 0 0 "Shell" 0 -1 1516735822996 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_burstwrap_increment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment " "Elaborating entity \"altera_merlin_burst_adapter_burstwrap_increment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_burstwrap_increment" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378276 ""}
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{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for VCSMX simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for VCSMX simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823007 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_min ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min " "Elaborating entity \"altera_merlin_burst_adapter_min\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_min" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 1004 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378281 ""}
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{ "Info" "synopsys_sim.setup" "" "2018.01.23.17:30:23 Info: synopsys/vcsmx" { } { } 0 0 "2018.01.23.17:30:23 Info: synopsys/vcsmx" 0 0 "Shell" 0 -1 1516735823054 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_subtractor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub " "Elaborating entity \"altera_merlin_burst_adapter_subtractor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "ab_sub" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378285 ""}
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{ "Info" "vcsmx_setup.sh" "" "2018.01.23.17:30:23 Info: synopsys/vcsmx" { } { } 0 0 "2018.01.23.17:30:23 Info: synopsys/vcsmx" 0 0 "Shell" 0 -1 1516735823361 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract " "Elaborating entity \"altera_merlin_burst_adapter_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "subtract" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 88 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378290 ""}
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{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for NCSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for NCSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823387 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_demux" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8813 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379228 ""}
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{ "Info" "cds.lib" "" "2018.01.23.17:30:23 Info: cadence" { } { } 0 0 "2018.01.23.17:30:23 Info: cadence" 0 0 "Shell" 0 -1 1516735823388 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_mux" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379239 ""}
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{ "Info" "hdl.var" "" "2018.01.23.17:30:23 Info: cadence" { } { } 0 0 "2018.01.23.17:30:23 Info: cadence" 0 0 "Shell" 0 -1 1516735823404 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 287 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379243 ""}
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{ "Info" "ncsim_setup.sh" "" "2018.01.23.17:30:23 Info: cadence" { } { } 0 0 "2018.01.23.17:30:23 Info: cadence" 0 0 "Shell" 0 -1 1516735823411 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379246 ""}
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{ "Info" " directory" "" "2018.01.23.17:30:23 Info: 32 .cds.lib files in cadence/cds_libs" { } { } 0 0 "2018.01.23.17:30:23 Info: 32 .cds.lib files in cadence/cds_libs" 0 0 "Shell" 0 -1 1516735823411 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_demux" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9485 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379398 ""}
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{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for RIVIERA simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for RIVIERA simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823422 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_mux" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10111 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379438 ""}
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{ "Info" "rivierapro_setup.tcl" "" "2018.01.23.17:30:23 Info: aldec" { } { } 0 0 "2018.01.23.17:30:23 Info: aldec" 0 0 "Shell" 0 -1 1516735823423 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 630 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379456 ""}
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{ "Info" "." "" "2018.01.23.17:30:23 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823423 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379459 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project." { } { } 0 0 "2018.01.23.17:30:23 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project." 0 0 "Shell" 0 -1 1516735823424 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "avalon_st_adapter" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10283 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379473 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Finished: Create Modelsim Project." { } { } 0 0 "2018.01.23.17:30:23 Info: Finished: Create Modelsim Project." 0 0 "Shell" 0 -1 1516735823424 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "error_adapter_0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 200 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379476 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Starting: Create block symbol file (.bsf)" { } { } 0 0 "2018.01.23.17:30:23 Info: Starting: Create block symbol file (.bsf)" 0 0 "Shell" 0 -1 1516735823425 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller ulight_fifo:u0\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "rst_controller" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 616 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379595 ""}
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{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:30:23 Info: Loading spw_fifo_ulight" { } { } 0 0 "2018.01.23.17:30:23 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735823430 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379600 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Reading input file" { } { } 0 0 "2018.01.23.17:30:23 Info: Reading input file" 0 0 "Shell" 0 -1 1516735823456 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1\"" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_req_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 220 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379604 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding auto_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823461 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spw_ulight_con_top_x spw_ulight_con_top_x:A_SPW_TOP " "Elaborating entity \"spw_ulight_con_top_x\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\"" { } { { "top_rtl/spw_fifo_ulight.v" "A_SPW_TOP" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 143 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379619 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module auto_start" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735823461 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "top_spw_ultra_light spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW " "Elaborating entity \"top_spw_ultra_light\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\"" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "SPW" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 101 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379622 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding clk_0 \[clock_source 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735823462 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSM_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM " "Elaborating entity \"FSM_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM\"" { } { { "../rtl/RTL_VB/top_spw_ultra_light.v" "FSM" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" 113 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379624 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module clk_0" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735823463 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX " "Elaborating entity \"RX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\"" { } { { "../rtl/RTL_VB/top_spw_ultra_light.v" "RX" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" 135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379628 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823464 ""}
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{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "rx_spw.v(508) " "Verilog HDL Case Statement information at rx_spw.v(508): all case item expressions in this case statement are onehot" { } { { "../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v" 508 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1503605379632 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX"}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module clock_sel" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735823464 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX " "Elaborating entity \"TX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\"" { } { { "../rtl/RTL_VB/top_spw_ultra_light.v" "TX" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379638 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823465 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_rx spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data " "Elaborating entity \"fifo_rx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\"" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "rx_data" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379644 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module counter_rx_fifo" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735823466 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_tx spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data " "Elaborating entity \"fifo_tx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\"" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "tx_data" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 130 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379648 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823466 ""}
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{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "counter fifo_tx.v(59) " "Verilog HDL Always Construct warning at fifo_tx.v(59): inferring latch(es) for variable \"counter\", which holds its previous value in one or more paths through the always construct" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1503605379651 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module counter_tx_fifo" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735823467 ""}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[0\] fifo_tx.v(59) " "Inferred latch for \"counter\[0\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823468 ""}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[1\] fifo_tx.v(59) " "Inferred latch for \"counter\[1\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_flag_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735823472 ""}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[2\] fifo_tx.v(59) " "Inferred latch for \"counter\[2\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823473 ""}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[3\] fifo_tx.v(59) " "Inferred latch for \"counter\[3\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_info" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735823474 ""}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[4\] fifo_tx.v(59) " "Inferred latch for \"counter\[4\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823475 ""}
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{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[5\] fifo_tx.v(59) " "Inferred latch for \"counter\[5\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_read_en_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735823475 ""}
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{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[5\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[5\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823476 ""}
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{ "Error" "EVRFX_VDB_NET_ANOTHER_DRIVER" "fifo_tx.v(59) " "Constant driver at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10029 "Constant driver at %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_rx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735823477 ""}
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{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[4\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[4\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823484 ""}
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{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[3\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[3\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_tx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735823484 ""}
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{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[2\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[2\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823486 ""}
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{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[1\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[1\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_rx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735823487 ""}
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{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[0\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[0\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823488 ""}
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{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data " "Can't elaborate user hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\"" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "tx_data" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 130 0 0 } } } 0 12152 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379660 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_tx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_tx_status" 0 0 "Shell" 0 -1 1516735823488 ""}
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{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg " "Generated suppressed messages file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605380524 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823489 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fsm_info" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fsm_info" 0 0 "Shell" 0 -1 1516735823490 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding hps_0 \[altera_hps 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735823491 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module hps_0" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735823496 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823514 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module led_pio_test" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735823515 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding link_disable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823516 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module link_disable" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735823517 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding link_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823518 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module link_start" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735823518 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding pll_0 \[altera_pll 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735823519 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module pll_0" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735823521 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823524 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_ready_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735823524 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823531 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735823531 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823532 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_data" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735823533 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:23 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:23 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823539 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_ready" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_ready" 0 0 "Shell" 0 -1 1516735823542 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823543 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module write_data_fifo_tx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735823543 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823544 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module write_en_tx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735823546 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Building connections" { } { } 0 0 "2018.01.23.17:30:23 Info: Building connections" 0 0 "Shell" 0 -1 1516735823547 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing connections" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing connections" 0 0 "Shell" 0 -1 1516735823550 ""}
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{ "Info" "" "" "2018.01.23.17:30:23 Info: Validating" { } { } 0 0 "2018.01.23.17:30:23 Info: Validating" 0 0 "Shell" 0 -1 1516735823560 ""}
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{ "Info" "" "" "2018.01.23.17:30:31 Info: Done reading input file" { } { } 0 0 "2018.01.23.17:30:31 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735831710 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833912 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833914 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735833914 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735833914 ""}
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{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735833914 ""}
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{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735833914 ""}
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{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735833915 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735833918 ""}
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{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735833918 ""}
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{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735833918 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735833918 ""}
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{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735833918 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""}
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{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: qsys-generate succeeded." { } { } 0 0 "2018.01.23.17:30:34 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735834875 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Finished: Create block symbol file (.bsf)" { } { } 0 0 "2018.01.23.17:30:34 Info: Finished: Create block symbol file (.bsf)" 0 0 "Shell" 0 -1 1516735834876 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info:" { } { } 0 0 "2018.01.23.17:30:34 Info:" 0 0 "Shell" 0 -1 1516735834876 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Starting: Create HDL design files for synthesis" { } { } 0 0 "2018.01.23.17:30:34 Info: Starting: Create HDL design files for synthesis" 0 0 "Shell" 0 -1 1516735834876 ""}
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{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:30:34 Info: Loading spw_fifo_ulight" { } { } 0 0 "2018.01.23.17:30:34 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735834883 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Reading input file" { } { } 0 0 "2018.01.23.17:30:34 Info: Reading input file" 0 0 "Shell" 0 -1 1516735834905 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding auto_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834909 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module auto_start" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735834909 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding clk_0 \[clock_source 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735834912 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module clk_0" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735834913 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834913 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module clock_sel" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735834914 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834915 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module counter_rx_fifo" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735834915 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834916 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module counter_tx_fifo" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735834917 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834918 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_flag_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735834918 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834919 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_info" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735834919 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834920 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_read_en_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735834921 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834921 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_rx_status" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735834922 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834923 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_tx_status" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735834925 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834926 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_rx_status" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735834926 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834927 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_tx_status\n2018.01.23.17:30:34 Info: Adding fsm_info \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module fsm_info\n2018.01.23.17:30:34 Info: Adding hps_0 \[altera_hps 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_tx_status\n2018.01.23.17:30:34 Info: Adding fsm_info \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module fsm_info\n2018.01.23.17:30:34 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735834929 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module hps_0" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735834934 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834943 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module led_pio_test" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735834944 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding link_disable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834946 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module link_disable" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735834946 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding link_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834948 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module link_start" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735834948 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding pll_0 \[altera_pll 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735834949 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module pll_0" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735834950 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834953 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_ready_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735834953 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834953 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735834953 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834954 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_data" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735834955 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:34 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_ready\n2018.01.23.17:30:34 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module write_data_fifo_tx" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:34 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_ready\n2018.01.23.17:30:34 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735834958 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834959 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module write_en_tx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735834959 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Building connections" { } { } 0 0 "2018.01.23.17:30:34 Info: Building connections" 0 0 "Shell" 0 -1 1516735834960 ""}
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{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing connections\n2018.01.23.17:30:34 Info: Validating" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing connections\n2018.01.23.17:30:34 Info: Validating" 0 0 "Shell" 0 -1 1516735834965 ""}
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{ "Info" "" "" "2018.01.23.17:30:41 Info: Done reading input file" { } { } 0 0 "2018.01.23.17:30:41 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735841270 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843344 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735843346 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735843346 ""}
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{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735843346 ""}
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{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735843346 ""}
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{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735843346 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735843348 ""}
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{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735843349 ""}
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{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735843349 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735843349 ""}
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{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735843349 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""}
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{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""}
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{ "Info" "" "" "2018.01.23.17:30:46 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for QUARTUS_SYNTH" { } { } 0 0 "2018.01.23.17:30:46 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for QUARTUS_SYNTH" 0 0 "Shell" 0 -1 1516735846790 ""}
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{ "Warning" "" "" "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" { } { } 0 0 "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" 0 0 "Shell" 0 -1 1516735856250 ""}
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{ "Warning" "" "" "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" { } { } 0 0 "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" 0 0 "Shell" 0 -1 1516735856250 ""}
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{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735858344 ""}
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{ "Info" "ulight_fifo_auto_start_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/" 0 0 "Shell" 0 -1 1516735858345 ""}
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{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735858460 ""}
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{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" 0 0 "Shell" 0 -1 1516735858461 ""}
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{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735858554 ""}
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{ "Info" "ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/" 0 0 "Shell" 0 -1 1516735858555 ""}
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{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735858668 ""}
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{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" 0 0 "Shell" 0 -1 1516735858670 ""}
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{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735858778 ""}
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{ "Info" "ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/" 0 0 "Shell" 0 -1 1516735858778 ""}
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{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735858895 ""}
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{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" 0 0 "Shell" 0 -1 1516735858898 ""}
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{ "Info" "" "" "2018.01.23.17:30:58 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" { } { } 0 0 "2018.01.23.17:30:58 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735858988 ""}
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{ "Info" "ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/" 0 0 "Shell" 0 -1 1516735858988 ""}
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{ "Info" "" "" "2018.01.23.17:30:59 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'" { } { } 0 0 "2018.01.23.17:30:59 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735859104 ""}
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{ "Info" "" "" "2018.01.23.17:30:59 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" { } { } 0 0 "2018.01.23.17:30:59 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" 0 0 "Shell" 0 -1 1516735859105 ""}
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{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735859198 ""}
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{ "Info" "ulight_fifo_data_info_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:59 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/" 0 0 "Shell" 0 -1 1516735859199 ""}
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{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735859311 ""}
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{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" 0 0 "Shell" 0 -1 1516735859312 ""}
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{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735859420 ""}
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{ "Info" "ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/" 0 0 "Shell" 0 -1 1516735859420 ""}
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{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735859548 ""}
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{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" 0 0 "Shell" 0 -1 1516735859548 ""}
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{ "Info" "" "" "2018.01.23.17:30:59 Info: hps_0: \"Running for module: hps_0\"" { } { } 0 0 "2018.01.23.17:30:59 Info: hps_0: \"Running for module: hps_0\"" 0 0 "Shell" 0 -1 1516735859549 ""}
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{ "Info" "" "" "2018.01.23.17:31:00 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:31:00 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735860279 ""}
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{ "Info" "" "" "2018.01.23.17:31:00 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:31:00 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735860805 ""}
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{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:31:00 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735860809 ""}
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{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:31:00 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735860825 ""}
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{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:31:00 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735860912 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" { } { } 0 0 "2018.01.23.17:31:01 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" 0 0 "Shell" 0 -1 1516735861270 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'" 0 0 "Shell" 0 -1 1516735861415 ""}
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{ "Info" "ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:01 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/" 0 0 "Shell" 0 -1 1516735861415 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'" 0 0 "Shell" 0 -1 1516735861536 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" 0 0 "Shell" 0 -1 1516735861537 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" { } { } 0 0 "2018.01.23.17:31:01 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" 0 0 "Shell" 0 -1 1516735861569 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735861676 ""}
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{ "Info" "ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:01 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/" 0 0 "Shell" 0 -1 1516735861676 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735861788 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" 0 0 "Shell" 0 -1 1516735861789 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735861875 ""}
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{ "Info" "ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/" 0 0 "Shell" 0 -1 1516735861876 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735861988 ""}
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{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" 0 0 "Shell" 0 -1 1516735861989 ""}
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{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735862097 ""}
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{ "Info" "ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/" 0 0 "Shell" 0 -1 1516735862097 ""}
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{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735862210 ""}
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{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" 0 0 "Shell" 0 -1 1516735862211 ""}
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{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863534 ""}
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{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863572 ""}
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{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863611 ""}
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{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863671 ""}
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{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863741 ""}
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{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863801 ""}
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{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863855 ""}
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{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863921 ""}
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{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863979 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864040 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864101 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864161 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864253 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864297 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864334 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864391 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864443 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864499 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864548 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864595 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864650 ""}
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{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864729 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" { } { } 0 0 "2018.01.23.17:31:06 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" 0 0 "Shell" 0 -1 1516735866289 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 0 "2018.01.23.17:31:06 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" 0 0 "Shell" 0 -1 1516735866293 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" { } { } 0 0 "2018.01.23.17:31:06 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" 0 0 "Shell" 0 -1 1516735866347 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" { } { } 0 0 "2018.01.23.17:31:06 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" 0 0 "Shell" 0 -1 1516735866457 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" 0 0 "Shell" 0 -1 1516735866458 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" { } { } 0 0 "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" 0 0 "Shell" 0 -1 1516735866460 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" 0 0 "Shell" 0 -1 1516735866461 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" 0 0 "Shell" 0 -1 1516735866463 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" { } { } 0 0 "2018.01.23.17:31:06 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" 0 0 "Shell" 0 -1 1516735866471 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" { } { } 0 0 "2018.01.23.17:31:06 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" 0 0 "Shell" 0 -1 1516735866481 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" { } { } 0 0 "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" 0 0 "Shell" 0 -1 1516735866484 ""}
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{ "Info" "altera_avalon_sc_fifo.v" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866484 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" 0 0 "Shell" 0 -1 1516735866489 ""}
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{ "Info" "altera_merlin_address_alignment.sv" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866490 ""}
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{ "Info" "altera_avalon_st_pipeline_base.v" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866491 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" 0 0 "Shell" 0 -1 1516735866497 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" 0 0 "Shell" 0 -1 1516735866516 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" 0 0 "Shell" 0 -1 1516735866526 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" 0 0 "Shell" 0 -1 1516735866542 ""}
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{ "Info" "altera_merlin_arbitrator.sv" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866544 ""}
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{ "Info" "" "" "2018.01.23.17:31:06 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" { } { } 0 0 "2018.01.23.17:31:06 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" 0 0 "Shell" 0 -1 1516735866567 ""}
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{ "Info" "" "" "2018.01.23.17:31:48 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" { } { } 0 0 "2018.01.23.17:31:48 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" 0 0 "Shell" 0 -1 1516735908549 ""}
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{ "Info" "" "" "2018.01.23.17:31:48 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" { } { } 0 0 "2018.01.23.17:31:48 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" 0 0 "Shell" 0 -1 1516735908640 ""}
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{ "Info" "" "" "2018.01.23.17:31:48 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 89 files" { } { } 0 0 "2018.01.23.17:31:48 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 89 files" 0 0 "Shell" 0 -1 1516735908640 ""}
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{ "Info" "" "" "2018.01.23.17:31:49 Info: qsys-generate succeeded." { } { } 0 0 "2018.01.23.17:31:49 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735909794 ""}
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{ "Info" "" "" "2018.01.23.17:31:49 Info: Finished: Create HDL design files for synthesis" { } { } 0 0 "2018.01.23.17:31:49 Info: Finished: Create HDL design files for synthesis" 0 0 "Shell" 0 -1 1516735909794 ""}
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{ "Info" "IIPMAN_IPRGEN_SUCCESSFUL" "Qsys ulight_fifo.qsys " "Completed upgrading IP component Qsys with file \"ulight_fifo.qsys\"" { } { } 0 11131 "Completed upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1516735919862 ""}
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{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "/home/felipe/intelFPGA_lite/17.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl " "Evaluation of Tcl script /home/felipe/intelFPGA_lite/17.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1516735929556 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 30 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1063 " "Peak virtual memory: 1063 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 23 17:32:09 2018 " "Processing ended: Tue Jan 23 17:32:09 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:09 " "Elapsed time: 00:05:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:08:27 " "Total CPU time (on all processors): 00:08:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1516735929557 ""}
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