| Line 1... |
Line 1... |
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1505474352323 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1517799546352 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1505474352334 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 08:19:12 2017 " "Processing started: Fri Sep 15 08:19:12 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1505474352334 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1505474352334 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1517799546385 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 5 00:59:06 2018 " "Processing started: Mon Feb 5 00:59:06 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1517799546385 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1517799546385 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1505474352334 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1517799546385 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1505474357626 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1517799550918 ""}
|
{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." { } { } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1505474357769 ""}
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{ "Info" "IQNETO_DONE_BOARD_STA_STAMP_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.mod /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.data " "Generated files \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.mod\" and \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.data\"" { } { } 0 199047 "Generated files \"%1!s!\" and \"%2!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1517799551540 ""}
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "spw_fifo_ulight.vo /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/simulation/modelsim/ simulation " "Generated file spw_fifo_ulight.vo in folder \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1505474360442 ""}
|
{ "Info" "IQNETO_DONE_BOARD_STA_STAMP_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.mod /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.data " "Generated files \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.mod\" and \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.data\"" { } { } 0 199047 "Generated files \"%1!s!\" and \"%2!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1517799551541 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1314 " "Peak virtual memory: 1314 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1505474360713 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 08:19:20 2017 " "Processing ended: Fri Sep 15 08:19:20 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1505474360713 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1505474360713 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1505474360713 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1505474360713 ""}
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{ "Info" "IQNETO_DONE_BOARD_STA_STAMP_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.mod /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.data " "Generated files \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.mod\" and \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.data\"" { } { } 0 199047 "Generated files \"%1!s!\" and \"%2!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1517799551541 ""}
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{ "Info" "IQNETO_DONE_BOARD_STA_STAMP_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.mod /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.data " "Generated files \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.mod\" and \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.data\"" { } { } 0 199047 "Generated files \"%1!s!\" and \"%2!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1517799551542 ""}
|
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{ "Info" "IQNETO_DONE_BOARD_STA_STAMP_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.mod /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.data " "Generated files \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.mod\" and \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.data\"" { } { } 0 199047 "Generated files \"%1!s!\" and \"%2!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1517799551543 ""}
|
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{ "Info" "IQNETO_GENERATED_HSPICE_FILES" "36 " "Generated 36 HSPICE Output files for board level analysis" { { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae26_led_5__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae26_led_5__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552966 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa23_led_7__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa23_led_7__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552966 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ag28_dout_a_out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ag28_dout_a_out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af20_sout_a_out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af20_sout_a_out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_w15_led_0__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_w15_led_0__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa24_led_1__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa24_led_1__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v16_led_2__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v16_led_2__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v15_led_3__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v15_led_3__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af26_led_4__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af26_led_4__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah17_key_0__in.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah17_key_0__in.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y16_led_6__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y16_led_6__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y13_fpga_clk1_50_in.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y13_fpga_clk1_50_in.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah16_key_1__in.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah16_key_1__in.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y15_din_a_in.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y15_din_a_in.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae20_sin_a_in.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae20_sin_a_in.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrt_calibrated.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrt_calibrated.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/output_delay_control.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/output_delay_control.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_vod_select.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_vod_select.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_preemphasis_select.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_preemphasis_select.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/slew_rate_control.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/slew_rate_control.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/drive_select_io.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/drive_select_io.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ss.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ss.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_input_load.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_input_load.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_tt.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_tt.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrt.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrt.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_load.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_load.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_rd.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_rd.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrs_calibrated.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrs_calibrated.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_load.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_load.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output_load.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output_load.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/package.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/package.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_load.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_load.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrs.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrs.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ff.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ff.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} } { } 0 199053 "Generated %1!d! HSPICE Output files for board level analysis" 0 0 "EDA Netlist Writer" 0 -1 1517799552966 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1244 " "Peak virtual memory: 1244 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1517799553201 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 5 00:59:13 2018 " "Processing ended: Mon Feb 5 00:59:13 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1517799553201 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1517799553201 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1517799553201 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1517799553201 ""}
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