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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1505473997024 ""}
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{ "Info" "IQCU_OPT_MODE_DESCRIPTION" "High Performance Effort timing performance increased compilation time " "High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time" { { "Info" "IQCU_OPT_MODE_OVERRIDE" "Fitter Effort Standard Fit " "Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)" { } { } 0 16304 "Mode behavior is affected by advanced setting %1!s! (default for this mode is %2!s!)" 0 0 "Design Software" 0 -1 1517799137877 ""} { "Info" "IQCU_OPT_MODE_OVERRIDE" "Physical Synthesis Effort Level Normal " "Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal)" { } { } 0 16304 "Mode behavior is affected by advanced setting %1!s! (default for this mode is %2!s!)" 0 0 "Design Software" 0 -1 1517799137877 ""} } { } 0 16303 "%1!s! optimization mode selected -- %2!s! will be prioritized at the potential cost of %3!s!" 0 0 "Fitter" 0 -1 1517799137877 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1505473997024 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1517799137898 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "spw_fifo_ulight 5CSEMA4U23C6 " "Selected device 5CSEMA4U23C6 for design \"spw_fifo_ulight\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1505473997081 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1517799137898 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1505473997158 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "spw_fifo_ulight 5CSEMA4U23C6 " "Selected device 5CSEMA4U23C6 for design \"spw_fifo_ulight\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1517799137969 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1505473997158 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1517799138047 ""}
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{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1505473997958 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1517799138047 ""}
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{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1505473998068 ""}
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{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1517799138850 ""}
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{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1505474002927 ""}
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{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1517799138937 ""}
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{ "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED_GROUP" "4 " "4 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins." { { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "dout_a dout_a(n) " "differential I/O pin \"dout_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"dout_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { dout_a } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" 1 { { 0 "dout_a" } { 0 "dout_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 801 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 805 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { dout_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1505474011939 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "sout_a sout_a(n) " "differential I/O pin \"sout_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"sout_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { sout_a } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" 1 { { 0 "sout_a" } { 0 "sout_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 10 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 802 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 807 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { sout_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1505474011939 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "din_a din_a(n) " "differential I/O pin \"din_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"din_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { din_a } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" 1 { { 0 "din_a" } { 0 "din_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 5 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 799 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 804 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { din_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1505474011939 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "sin_a sin_a(n) " "differential I/O pin \"sin_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"sin_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { sin_a } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" 1 { { 0 "sin_a" } { 0 "sin_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 6 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 800 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 806 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { sin_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1505474011939 ""} } { } 0 184025 "%1!d! differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins." 0 0 "Fitter" 0 -1 1505474011939 ""}
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{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1517799143937 ""}
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{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1505474012167 ""}
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{ "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED_GROUP" "4 " "4 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins." { { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "dout_a dout_a(n) " "differential I/O pin \"dout_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"dout_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { dout_a } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "dout_a" } { 0 "dout_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 818 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 822 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { dout_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1517799153225 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "sout_a sout_a(n) " "differential I/O pin \"sout_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"sout_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { sout_a } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "sout_a" } { 0 "sout_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 10 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 819 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 824 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { sout_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1517799153225 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "din_a din_a(n) " "differential I/O pin \"din_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"din_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { din_a } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "din_a" } { 0 "din_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 5 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 816 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 821 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { din_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1517799153225 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "sin_a sin_a(n) " "differential I/O pin \"sin_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"sin_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { sin_a } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "sin_a" } { 0 "sin_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 6 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 817 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 823 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { sin_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1517799153225 ""} } { } 0 184025 "%1!d! differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins." 0 0 "Fitter" 0 -1 1517799153225 ""}
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{ "Info" "ICCLK_CLOCKS_TOP" "2 s (2 global) " "Promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|h2f_rst_n\[0\]~CLKENA0 3 global CLKCTRL_G10 " "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|h2f_rst_n\[0\]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G10" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1505474012512 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|divclk\[0\]~CLKENA0 24 global CLKCTRL_G11 " "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|divclk\[0\]~CLKENA0 with 24 fanout uses global clock CLKCTRL_G11" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1505474012512 ""} } { } 0 11178 "Promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1505474012512 ""}
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{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1517799153477 ""}
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{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "2 s (2 global) " "Automatically promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "FPGA_CLK1_50~inputCLKENA0 3124 global CLKCTRL_G5 " "FPGA_CLK1_50~inputCLKENA0 with 3124 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1505474012512 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out~CLKENA0 3025 global CLKCTRL_G3 " "ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out~CLKENA0 with 3025 fanout uses global clock CLKCTRL_G3" { { "Info" "ICCLK_UNLOCKED_FOR_VPR" "" "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" { } { } 0 12525 "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" 0 0 "Design Software" 0 -1 1505474012512 ""} } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1505474012512 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1505474012512 ""}
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{ "Warning" "WCCLK_MISSING_PLL_COMPENSATED_CLOCK" "FRACTIONALPLL_X68_Y1_N0 " "PLL(s) placed in location FRACTIONALPLL_X68_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks" { { "Info" "ICCLK_PLL_NAME" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\|fpll " "PLL ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\|fpll" { } { } 0 177008 "PLL %1!s!" 0 0 "Design Software" 0 -1 1517799153655 ""} } { } 0 177007 "PLL(s) placed in location %1!s! do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks" 0 0 "Fitter" 0 -1 1517799153655 ""}
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{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474012514 ""}
|
{ "Info" "ICCLK_CLOCKS_TOP" "2 s (2 global) " "Promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|h2f_rst_n\[0\]~CLKENA0 3 global CLKCTRL_G11 " "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|h2f_rst_n\[0\]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G11" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1517799153786 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|divclk\[0\]~CLKENA0 24 global CLKCTRL_G8 " "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|divclk\[0\]~CLKENA0 with 24 fanout uses global clock CLKCTRL_G8" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1517799153786 ""} } { } 0 11178 "Promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1517799153786 ""}
|
{ "Info" "ISTA_SDC_FOUND" "sdc/spw_fifo_ulight.out.sdc " "Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1505474015751 ""}
|
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "FPGA_CLK1_50~inputCLKENA0 3068 global CLKCTRL_G4 " "FPGA_CLK1_50~inputCLKENA0 with 3068 fanout uses global clock CLKCTRL_G4" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1517799153786 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1517799153786 ""}
|
{ "Info" "ISTA_SDC_FOUND" "ulight_fifo/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1505474015838 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799153787 ""}
|
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataa to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0 from: dataa to: combout " "Cell: m_x\|always3~0 from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Fitter" 0 -1 1505474015904 ""}
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{ "Info" "ISTA_SDC_FOUND" "sdc/spw_fifo_ulight.out.sdc " "Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1517799156769 ""}
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{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "Fitter" 0 -1 1505474015990 ""}
|
{ "Info" "ISTA_SDC_FOUND" "ulight_fifo/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1517799156861 ""}
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{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1505474015998 ""}
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{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataa to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|comb from: datab to: combout " "Cell: m_x\|comb from: datab to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Fitter" 0 -1 1517799156990 ""}
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{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 4.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 4.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 3.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 3.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 3.000 din_a " " 3.000 din_a" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 FPGA_CLK1_50 " " 10.000 FPGA_CLK1_50" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 3.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " " 3.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1505474015998 ""}
|
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "Fitter" 0 -1 1517799157110 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1505474016303 ""}
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{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1517799157116 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1505474016328 ""}
|
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 10.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 2.500 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 2.500 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 4.000 din_a " " 4.000 din_a" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 FPGA_CLK1_50 " " 20.000 FPGA_CLK1_50" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 4.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 4.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1517799157116 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1505474016383 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1517799157465 ""}
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{ "Info" "IFSAC_FSAC_OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING_OFF" "" "Fitter will not automatically pack the registers into I/Os." { } { } 0 176222 "Fitter will not automatically pack the registers into I/Os." 0 0 "Fitter" 0 -1 1505474016383 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1517799157488 ""}
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{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1505474016428 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1517799157542 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1505474016429 ""}
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{ "Info" "IFSAC_FSAC_OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING_EXTRA_EFFORT" "" "The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os." { } { } 0 176221 "The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os." 0 0 "Fitter" 0 -1 1517799157542 ""}
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{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1505474016452 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1517799157589 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1505474017532 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1517799157589 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1505474017561 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1505474017561 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1517799157614 ""}
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{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474017705 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1517799158752 ""}
|
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474018213 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "5 I/O output buffer " "Packed 5 registers into blocks of type I/O output buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Design Software" 0 -1 1517799158778 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "5 " "Created 5 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Design Software" 0 -1 1517799158778 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1517799158778 ""}
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{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:16 " "Fitter preparation operations ending: elapsed time is 00:00:16" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474018538 ""}
|
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799159580 ""}
|
{ "Warning" "WFITAPI_FITAPI_VPR_PLACEMENT_EFFORT_MULTIPLIER_USED_WITH_RETRY_LOOP" "90.0 " "Design uses Placement Effort Multiplier = 90.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt." { } { } 0 170136 "Design uses Placement Effort Multiplier = %1!s!. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt." 0 0 "Fitter" 0 -1 1505474025663 ""}
|
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799160101 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1505474025664 ""}
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{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" { } { } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Fitter" 0 -1 1517799160284 ""}
|
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474026402 ""}
|
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" { } { } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Fitter" 0 -1 1517799161364 ""}
|
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474026913 ""}
|
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 662 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 662 ps" { } { } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Fitter" 0 -1 1517799164219 ""}
|
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1505474028148 ""}
|
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" { } { } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Fitter" 0 -1 1517799164228 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:28 " "Fitter placement preparation operations ending: elapsed time is 00:00:28" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474053768 ""}
|
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" { } { } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Fitter" 0 -1 1517799167114 ""}
|
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474053966 ""}
|
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:09 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:09" { } { } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Fitter" 0 -1 1517799168860 ""}
|
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474054534 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1517799169216 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1505474083911 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1517799169362 ""}
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{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1505474198604 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1517799169362 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:01:55 " "Fitter placement operations ending: elapsed time is 00:01:55" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474198605 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1517799169394 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1505474201404 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1517799173172 ""}
|
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474205572 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1517799173208 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1517799173208 ""}
|
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474206099 ""}
|
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:30 " "Fitter preparation operations ending: elapsed time is 00:00:30" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799173546 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 " "Router estimated average interconnect usage is 3% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X11_Y24 X22_Y36 " "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y24 to location X22_Y36" { } { { "loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 1 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y24 to location X22_Y36"} { { 12 { 0 ""} 11 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1505474225170 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1505474225170 ""}
|
{ "Warning" "WFITAPI_FITAPI_VPR_PLACEMENT_EFFORT_MULTIPLIER_USED_WITH_RETRY_LOOP" "4.0 " "Design uses Placement Effort Multiplier = 4.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt." { } { } 0 170136 "Design uses Placement Effort Multiplier = %1!s!. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt." 0 0 "Fitter" 0 -1 1517799180874 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1505474245410 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1505474245410 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1517799180875 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:40 " "Fitter routing operations ending: elapsed time is 00:00:40" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474245414 ""}
|
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799181783 ""}
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 16.50 " "Total time spent on timing analysis during the Fitter is 16.50 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1505474262288 ""}
|
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799182302 ""}
|
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:05 " "Fitter post-fit operations ending: elapsed time is 00:00:05" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474267685 ""}
|
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1517799183901 ""}
|
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1505474268262 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:35 " "Fitter placement preparation operations ending: elapsed time is 00:00:35" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799216311 ""}
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg " "Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1505474269280 ""}
|
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799216566 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2064 " "Peak virtual memory: 2064 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1505474271108 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 08:17:51 2017 " "Processing ended: Fri Sep 15 08:17:51 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1505474271108 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:04:44 " "Elapsed time: 00:04:44" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1505474271108 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:08:19 " "Total CPU time (on all processors): 00:08:19" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1505474271108 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1505474271108 ""}
|
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799217081 ""}
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1517799245270 ""}
|
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1517799302561 ""}
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:58 " "Fitter placement operations ending: elapsed time is 00:00:58" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799302561 ""}
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1517799307763 ""}
|
|
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799311838 ""}
|
|
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799312357 ""}
|
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X46_Y0 X56_Y11 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11" { } { { "loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11"} { { 12 { 0 ""} 46 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1517799337080 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1517799337080 ""}
|
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization." { } { } 0 170202 "The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0 "Fitter" 0 -1 1517799387310 ""}
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:01:16 " "Fitter routing operations ending: elapsed time is 00:01:16" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799387315 ""}
|
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 27.50 " "Total time spent on timing analysis during the Fitter is 27.50 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1517799398841 ""}
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1517799399079 ""}
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1517799405514 ""}
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1517799405523 ""}
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1517799411502 ""}
|
|
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:38 " "Fitter post-fit operations ending: elapsed time is 00:00:38" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799436539 ""}
|
|
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1517799437203 ""}
|
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg " "Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1517799437984 ""}
|
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{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2473 " "Peak virtual memory: 2473 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1517799440640 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 5 00:57:20 2018 " "Processing ended: Mon Feb 5 00:57:20 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1517799440640 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:09 " "Elapsed time: 00:05:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1517799440640 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:08:50 " "Total CPU time (on all processors): 00:08:50" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1517799440640 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1517799440640 ""}
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