| Line 151... |
Line 151... |
state.ST_IDLE 0 0 0 0
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state.ST_IDLE 0 0 0 0
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state.ST_COMP_TRANS 1 0 0 1
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state.ST_COMP_TRANS 1 0 0 1
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state.ST_UNCOMP_TRANS 1 0 1 0
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state.ST_UNCOMP_TRANS 1 0 1 0
|
state.ST_UNCOMP_WR_SUBBURST 1 1 0 0
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state.ST_UNCOMP_WR_SUBBURST 1 1 0 0
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State Machine - |SPW_ULIGHT_FIFO|detector_tokens:m_x|state_data_process
|
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Name state_data_process.01
|
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state_data_process.00 0
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state_data_process.01 1
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot
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Name state_open_slot.00 state_open_slot.10 state_open_slot.01
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state_open_slot.00 0 0 0
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state_open_slot.01 1 0 1
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state_open_slot.10 1 1 0
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write
|
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Name state_data_write.00 state_data_write.10 state_data_write.01
|
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state_data_write.00 0 0 0
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state_data_write.01 1 0 1
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state_data_write.10 1 1 0
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read
|
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Name state_data_read.00 state_data_read.10 state_data_read.01
|
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state_data_read.00 0 0 0
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state_data_read.01 1 0 1
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state_data_read.10 1 1 0
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State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state
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State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state
|
Name dps_current_state.PHASE_DONE_LOW_0 dps_current_state.PHASE_DONE_LOW_4 dps_current_state.PHASE_DONE_LOW_3 dps_current_state.PHASE_DONE_LOW_2 dps_current_state.PHASE_DONE_LOW_1 dps_current_state.PHASE_DONE_HIGH
|
Name dps_current_state.PHASE_DONE_LOW_0 dps_current_state.PHASE_DONE_LOW_4 dps_current_state.PHASE_DONE_LOW_3 dps_current_state.PHASE_DONE_LOW_2 dps_current_state.PHASE_DONE_LOW_1 dps_current_state.PHASE_DONE_HIGH
|
dps_current_state.PHASE_DONE_HIGH 0 0 0 0 0 0
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dps_current_state.PHASE_DONE_HIGH 0 0 0 0 0 0
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dps_current_state.PHASE_DONE_LOW_1 0 0 0 0 1 1
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dps_current_state.PHASE_DONE_LOW_1 0 0 0 0 1 1
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dps_current_state.PHASE_DONE_LOW_2 0 0 0 1 0 1
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dps_current_state.PHASE_DONE_LOW_2 0 0 0 1 0 1
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dps_current_state.PHASE_DONE_LOW_3 0 0 1 0 0 1
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dps_current_state.PHASE_DONE_LOW_3 0 0 1 0 0 1
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dps_current_state.PHASE_DONE_LOW_4 0 1 0 0 0 1
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dps_current_state.PHASE_DONE_LOW_4 0 1 0 0 0 1
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dps_current_state.PHASE_DONE_LOW_0 1 0 0 0 0 1
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dps_current_state.PHASE_DONE_LOW_0 1 0 0 0 0 1
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|state_tx
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read
|
Name state_tx.tx_spw_start state_tx.tx_spw_full state_tx.tx_spw_null_fct state_tx.tx_spw_null
|
Name state_data_read.11 state_data_read.10 state_data_read.01 state_data_read.00
|
state_tx.tx_spw_start 0 0 0 0
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state_data_read.00 0 0 0 0
|
state_tx.tx_spw_null 1 0 0 1
|
state_data_read.01 0 0 1 1
|
state_tx.tx_spw_null_fct 1 0 1 0
|
state_data_read.10 0 1 0 1
|
state_tx.tx_spw_full 1 1 0 0
|
state_data_read.11 1 0 0 1
|
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|last_type
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx
|
Name last_type.TIMEC last_type.DATA last_type.EEP last_type.EOP last_type.FCT last_type.NULL
|
Name state_tx.tx_spw_time_code_c state_tx.tx_spw_data_c_0 state_tx.tx_spw_data_c state_tx.tx_spw_fct_c state_tx.tx_spw_null_c state_tx.tx_spw_fct state_tx.tx_spw_null state_tx.tx_spw_start
|
last_type.NULL 0 0 0 0 0 0
|
state_tx.tx_spw_start 0 0 0 0 0 0 0 0
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last_type.FCT 0 0 0 0 1 1
|
state_tx.tx_spw_null 0 0 0 0 0 0 1 1
|
last_type.EOP 0 0 0 1 0 1
|
state_tx.tx_spw_fct 0 0 0 0 0 1 0 1
|
last_type.EEP 0 0 1 0 0 1
|
state_tx.tx_spw_null_c 0 0 0 0 1 0 0 1
|
last_type.DATA 0 1 0 0 0 1
|
state_tx.tx_spw_fct_c 0 0 0 1 0 0 0 1
|
last_type.TIMEC 1 0 0 0 0 1
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state_tx.tx_spw_data_c 0 0 1 0 0 0 0 1
|
|
state_tx.tx_spw_data_c_0 0 1 0 0 0 0 0 1
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state_tx.tx_spw_time_code_c 1 0 0 0 0 0 0 1
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|
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send
|
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Name state_fct_send.001
|
|
state_fct_send.000 0
|
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state_fct_send.001 1
|
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|
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p
|
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Name state_fct_send_p.000 state_fct_send_p.010 state_fct_send_p.001
|
|
state_fct_send_p.001 0 0 0
|
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state_fct_send_p.000 1 0 1
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state_fct_send_p.010 0 1 1
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p
|
|
Name state_fct_p.011 state_fct_p.010 state_fct_p.001 state_fct_p.000 state_fct_p.100
|
|
state_fct_p.000 0 0 0 0 0
|
|
state_fct_p.001 0 0 1 1 0
|
|
state_fct_p.010 0 1 0 1 0
|
|
state_fct_p.011 1 0 0 1 0
|
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state_fct_p.100 0 0 0 1 1
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write
|
|
Name state_data_write.00 state_data_write.10 state_data_write.01
|
|
state_data_write.00 0 0 0
|
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state_data_write.01 1 0 1
|
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state_data_write.10 1 1 0
|
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|
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive
|
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Name state_fct_receive.011 state_fct_receive.010 state_fct_receive.001 state_fct_receive.000 state_fct_receive.100
|
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state_fct_receive.000 0 0 0 0 0
|
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state_fct_receive.001 0 0 1 1 0
|
|
state_fct_receive.010 0 1 0 1 0
|
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state_fct_receive.011 1 0 0 1 0
|
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state_fct_receive.100 0 0 0 1 1
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State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm
|
Name state_fsm.error_reset state_fsm.run state_fsm.connecting state_fsm.started state_fsm.ready state_fsm.error_wait
|
Name state_fsm.error_reset state_fsm.run state_fsm.connecting state_fsm.started state_fsm.ready state_fsm.error_wait
|
state_fsm.error_reset 0 0 0 0 0 0
|
state_fsm.error_reset 0 0 0 0 0 0
|
state_fsm.error_wait 1 0 0 0 0 1
|
state_fsm.error_wait 1 0 0 0 0 1
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