| Line 1... |
Line 1... |
Fitter report for spw_fifo_ulight
|
Fitter report for spw_fifo_ulight
|
Thu Aug 24 22:41:04 2017
|
Fri Sep 15 08:17:49 2017
|
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition
|
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition
|
|
|
|
|
---------------------
|
---------------------
|
; Table of Contents ;
|
; Table of Contents ;
|
| Line 27... |
Line 27... |
19. Fitter Resource Utilization by Entity
|
19. Fitter Resource Utilization by Entity
|
20. Delay Chain Summary
|
20. Delay Chain Summary
|
21. Pad To Core Delay Chain Fanout
|
21. Pad To Core Delay Chain Fanout
|
22. Control Signals
|
22. Control Signals
|
23. Global & Other Fast Signals
|
23. Global & Other Fast Signals
|
24. Fitter RAM Summary
|
24. Non-Global High Fan-Out Signals
|
25. Routing Usage Summary
|
25. Routing Usage Summary
|
26. I/O Rules Summary
|
26. I/O Rules Summary
|
27. I/O Rules Details
|
27. I/O Rules Details
|
28. I/O Rules Matrix
|
28. I/O Rules Matrix
|
29. Fitter Device Options
|
29. Fitter Device Options
|
| Line 64... |
Line 64... |
|
|
|
|
+-------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------+
|
; Fitter Summary ;
|
; Fitter Summary ;
|
+---------------------------------+---------------------------------------------+
|
+---------------------------------+---------------------------------------------+
|
; Fitter Status ; Successful - Thu Aug 24 22:41:04 2017 ;
|
; Fitter Status ; Successful - Fri Sep 15 08:17:49 2017 ;
|
; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;
|
; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;
|
; Revision Name ; spw_fifo_ulight ;
|
; Revision Name ; spw_fifo_ulight ;
|
; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
|
; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
|
; Family ; Cyclone V ;
|
; Family ; Cyclone V ;
|
; Device ; 5CSEMA4U23C6 ;
|
; Device ; 5CSEMA4U23C6 ;
|
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
; Logic utilization (in ALMs) ; 2,724 / 15,880 ( 17 % ) ;
|
; Logic utilization (in ALMs) ; 3,209 / 15,880 ( 20 % ) ;
|
; Total registers ; 3603 ;
|
; Total registers ; 4692 ;
|
; Total pins ; 19 / 314 ( 6 % ) ;
|
; Total pins ; 19 / 314 ( 6 % ) ;
|
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
; Total block memory bits ; 1,152 / 2,764,800 ( < 1 % ) ;
|
; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;
|
; Total RAM Blocks ; 2 / 270 ( < 1 % ) ;
|
; Total RAM Blocks ; 0 / 270 ( 0 % ) ;
|
; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
|
; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
|
; Total HSSI RX PCSs ; 0 ;
|
; Total HSSI RX PCSs ; 0 ;
|
; Total HSSI PMA RX Deserializers ; 0 ;
|
; Total HSSI PMA RX Deserializers ; 0 ;
|
; Total HSSI TX PCSs ; 0 ;
|
; Total HSSI TX PCSs ; 0 ;
|
; Total HSSI PMA TX Serializers ; 0 ;
|
; Total HSSI PMA TX Serializers ; 0 ;
|
| Line 96... |
Line 96... |
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
|
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
|
; Device ; 5CSEMA4U23C6 ; ;
|
; Device ; 5CSEMA4U23C6 ; ;
|
; Minimum Core Junction Temperature ; 0 ; ;
|
; Minimum Core Junction Temperature ; 0 ; ;
|
; Maximum Core Junction Temperature ; 85 ; ;
|
; Maximum Core Junction Temperature ; 85 ; ;
|
; Router Timing Optimization Level ; MAXIMUM ; Normal ;
|
; Router Timing Optimization Level ; MAXIMUM ; Normal ;
|
; Placement Effort Multiplier ; 40.0 ; 1.0 ;
|
; Placement Effort Multiplier ; 90.0 ; 1.0 ;
|
; PowerPlay Power Optimization During Fitting ; Extra effort ; Normal compilation ;
|
; PowerPlay Power Optimization During Fitting ; Extra effort ; Normal compilation ;
|
; Optimize IOC Register Placement for Timing ; Off ; Normal ;
|
; Optimize IOC Register Placement for Timing ; Off ; Normal ;
|
|
; Fitter Initial Placement Seed ; 893763639 ; 1 ;
|
; Auto Delay Chains ; Off ; On ;
|
; Auto Delay Chains ; Off ; On ;
|
; Physical Synthesis Effort Level ; Extra ; Normal ;
|
; Physical Synthesis Effort Level ; Extra ; Normal ;
|
; Logic Cell Insertion - Logic Duplication ; Off ; Auto ;
|
; Logic Cell Insertion - Logic Duplication ; Off ; Auto ;
|
; Auto Register Duplication ; Off ; Auto ;
|
; Auto Register Duplication ; Off ; Auto ;
|
; Use smart compilation ; Off ; Off ;
|
; Use smart compilation ; Off ; Off ;
|
| Line 119... |
Line 120... |
; Optimize Timing ; Normal compilation ; Normal compilation ;
|
; Optimize Timing ; Normal compilation ; Normal compilation ;
|
; Optimize Timing for ECOs ; Off ; Off ;
|
; Optimize Timing for ECOs ; Off ; Off ;
|
; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
|
; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
|
; Final Placement Optimizations ; Automatically ; Automatically ;
|
; Final Placement Optimizations ; Automatically ; Automatically ;
|
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
|
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
|
; Fitter Initial Placement Seed ; 1 ; 1 ;
|
|
; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
|
; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
|
; Weak Pull-Up Resistor ; Off ; Off ;
|
; Weak Pull-Up Resistor ; Off ; Off ;
|
; Enable Bus-Hold Circuitry ; Off ; Off ;
|
; Enable Bus-Hold Circuitry ; Off ; Off ;
|
; Auto Packed Registers ; Auto ; Auto ;
|
; Auto Packed Registers ; Auto ; Auto ;
|
; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
|
; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
|
| Line 154... |
Line 154... |
; Processors ; Number ;
|
; Processors ; Number ;
|
+----------------------------+-------------+
|
+----------------------------+-------------+
|
; Number detected on machine ; 4 ;
|
; Number detected on machine ; 4 ;
|
; Maximum allowed ; 2 ;
|
; Maximum allowed ; 2 ;
|
; ; ;
|
; ; ;
|
; Average used ; 1.03 ;
|
; Average used ; 1.02 ;
|
; Maximum used ; 2 ;
|
; Maximum used ; 2 ;
|
; ; ;
|
; ; ;
|
; Usage by Processor ; % Time Used ;
|
; Usage by Processor ; % Time Used ;
|
; Processor 1 ; 100.0% ;
|
; Processor 1 ; 100.0% ;
|
; Processor 2 ; 2.6% ;
|
; Processor 2 ; 2.2% ;
|
+----------------------------+-------------+
|
+----------------------------+-------------+
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Fitter Netlist Optimizations ;
|
; Fitter Netlist Optimizations ;
|
| Line 191... |
Line 191... |
; Incremental Compilation Preservation Summary ;
|
; Incremental Compilation Preservation Summary ;
|
+---------------------+---------------------+----------------------------+--------------------------+
|
+---------------------+---------------------+----------------------------+--------------------------+
|
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
|
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
|
+---------------------+---------------------+----------------------------+--------------------------+
|
+---------------------+---------------------+----------------------------+--------------------------+
|
; Placement (by node) ; ; ; ;
|
; Placement (by node) ; ; ; ;
|
; -- Requested ; 0.00 % ( 0 / 8370 ) ; 0.00 % ( 0 / 8370 ) ; 0.00 % ( 0 / 8370 ) ;
|
; -- Requested ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ;
|
; -- Achieved ; 0.00 % ( 0 / 8370 ) ; 0.00 % ( 0 / 8370 ) ; 0.00 % ( 0 / 8370 ) ;
|
; -- Achieved ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Routing (by net) ; ; ; ;
|
; Routing (by net) ; ; ; ;
|
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
+---------------------+---------------------+----------------------------+--------------------------+
|
+---------------------+---------------------+----------------------------+--------------------------+
|
| Line 215... |
Line 215... |
+------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------+
|
; Incremental Compilation Placement Preservation ;
|
; Incremental Compilation Placement Preservation ;
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
|
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
; Top ; 0.00 % ( 0 / 8352 ) ; N/A ; Source File ; N/A ; ;
|
; Top ; 0.00 % ( 0 / 9951 ) ; N/A ; Source File ; N/A ; ;
|
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 18 ) ; N/A ; Source File ; N/A ; ;
|
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 18 ) ; N/A ; Source File ; N/A ; ;
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
|
|
|
|
+--------------+
|
+--------------+
|
| Line 231... |
Line 231... |
+---------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------+
|
; Fitter Resource Usage Summary ;
|
; Fitter Resource Usage Summary ;
|
+-------------------------------------------------------------+-----------------------+-------+
|
+-------------------------------------------------------------+-----------------------+-------+
|
; Resource ; Usage ; % ;
|
; Resource ; Usage ; % ;
|
+-------------------------------------------------------------+-----------------------+-------+
|
+-------------------------------------------------------------+-----------------------+-------+
|
; Logic utilization (ALMs needed / total ALMs on device) ; 2,724 / 15,880 ; 17 % ;
|
; Logic utilization (ALMs needed / total ALMs on device) ; 3,209 / 15,880 ; 20 % ;
|
; ALMs needed [=A-B+C] ; 2,724 ; ;
|
; ALMs needed [=A-B+C] ; 3,209 ; ;
|
; [A] ALMs used in final placement [=a+b+c+d] ; 2,988 / 15,880 ; 19 % ;
|
; [A] ALMs used in final placement [=a+b+c+d] ; 3,800 / 15,880 ; 24 % ;
|
; [a] ALMs used for LUT logic and registers ; 1,492 ; ;
|
; [a] ALMs used for LUT logic and registers ; 1,607 ; ;
|
; [b] ALMs used for LUT logic ; 1,197 ; ;
|
; [b] ALMs used for LUT logic ; 1,468 ; ;
|
; [c] ALMs used for registers ; 299 ; ;
|
; [c] ALMs used for registers ; 725 ; ;
|
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
|
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
|
; [B] Estimate of ALMs recoverable by dense packing ; 270 / 15,880 ; 2 % ;
|
; [B] Estimate of ALMs recoverable by dense packing ; 601 / 15,880 ; 4 % ;
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 6 / 15,880 ; < 1 % ;
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 10 / 15,880 ; < 1 % ;
|
; [a] Due to location constrained logic ; 0 ; ;
|
; [a] Due to location constrained logic ; 0 ; ;
|
; [b] Due to LAB-wide signal conflicts ; 2 ; ;
|
; [b] Due to LAB-wide signal conflicts ; 5 ; ;
|
; [c] Due to LAB input limits ; 4 ; ;
|
; [c] Due to LAB input limits ; 5 ; ;
|
; [d] Due to virtual I/Os ; 0 ; ;
|
; [d] Due to virtual I/Os ; 0 ; ;
|
; ; ; ;
|
; ; ; ;
|
; Difficulty packing design ; Low ; ;
|
; Difficulty packing design ; Low ; ;
|
; ; ; ;
|
; ; ; ;
|
; Total LABs: partially or completely used ; 346 / 1,588 ; 22 % ;
|
; Total LABs: partially or completely used ; 455 / 1,588 ; 29 % ;
|
; -- Logic LABs ; 346 ; ;
|
; -- Logic LABs ; 455 ; ;
|
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
|
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
|
; ; ; ;
|
; ; ; ;
|
; Combinational ALUT usage for logic ; 4,775 ; ;
|
; Combinational ALUT usage for logic ; 5,301 ; ;
|
; -- 7 input functions ; 57 ; ;
|
; -- 7 input functions ; 59 ; ;
|
; -- 6 input functions ; 743 ; ;
|
; -- 6 input functions ; 1,198 ; ;
|
; -- 5 input functions ; 834 ; ;
|
; -- 5 input functions ; 825 ; ;
|
; -- 4 input functions ; 1,357 ; ;
|
; -- 4 input functions ; 1,419 ; ;
|
; -- <=3 input functions ; 1,784 ; ;
|
; -- <=3 input functions ; 1,800 ; ;
|
; Combinational ALUT usage for route-throughs ; 136 ; ;
|
; Combinational ALUT usage for route-throughs ; 473 ; ;
|
; ; ; ;
|
; ; ; ;
|
; Dedicated logic registers ; 3,603 ; ;
|
; Dedicated logic registers ; 4,692 ; ;
|
; -- By type: ; ; ;
|
; -- By type: ; ; ;
|
; -- Primary logic registers ; 3,581 / 31,760 ; 11 % ;
|
; -- Primary logic registers ; 4,664 / 31,760 ; 15 % ;
|
; -- Secondary logic registers ; 22 / 31,760 ; < 1 % ;
|
; -- Secondary logic registers ; 28 / 31,760 ; < 1 % ;
|
; -- By function: ; ; ;
|
; -- By function: ; ; ;
|
; -- Design implementation registers ; 3,603 ; ;
|
; -- Design implementation registers ; 4,692 ; ;
|
; -- Routing optimization registers ; 0 ; ;
|
; -- Routing optimization registers ; 0 ; ;
|
; ; ; ;
|
; ; ; ;
|
; Virtual pins ; 0 ; ;
|
; Virtual pins ; 0 ; ;
|
; I/O pins ; 19 / 314 ; 6 % ;
|
; I/O pins ; 19 / 314 ; 6 % ;
|
; -- Clock pins ; 2 / 6 ; 33 % ;
|
; -- Clock pins ; 2 / 6 ; 33 % ;
|
| Line 299... |
Line 299... |
; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
|
; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
|
; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
|
; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
|
; -- UART ; 0 / 2 ( 0 % ) ; ;
|
; -- UART ; 0 / 2 ( 0 % ) ; ;
|
; -- USB ; 0 / 2 ( 0 % ) ; ;
|
; -- USB ; 0 / 2 ( 0 % ) ; ;
|
; ; ; ;
|
; ; ; ;
|
; M10K blocks ; 2 / 270 ; < 1 % ;
|
; M10K blocks ; 0 / 270 ; 0 % ;
|
; Total MLAB memory bits ; 0 ; ;
|
; Total MLAB memory bits ; 0 ; ;
|
; Total block memory bits ; 1,152 / 2,764,800 ; < 1 % ;
|
; Total block memory bits ; 0 / 2,764,800 ; 0 % ;
|
; Total block memory implementation bits ; 20,480 / 2,764,800 ; < 1 % ;
|
; Total block memory implementation bits ; 0 / 2,764,800 ; 0 % ;
|
; ; ; ;
|
; ; ; ;
|
; Total DSP Blocks ; 0 / 84 ; 0 % ;
|
; Total DSP Blocks ; 0 / 84 ; 0 % ;
|
; ; ; ;
|
; ; ; ;
|
; Fractional PLLs ; 1 / 5 ; 20 % ;
|
; Fractional PLLs ; 1 / 5 ; 20 % ;
|
; Global signals ; 4 ; ;
|
; Global signals ; 4 ; ;
|
| Line 320... |
Line 320... |
; CRC blocks ; 0 / 1 ; 0 % ;
|
; CRC blocks ; 0 / 1 ; 0 % ;
|
; Remote update blocks ; 0 / 1 ; 0 % ;
|
; Remote update blocks ; 0 / 1 ; 0 % ;
|
; Oscillator blocks ; 0 / 1 ; 0 % ;
|
; Oscillator blocks ; 0 / 1 ; 0 % ;
|
; Impedance control blocks ; 0 / 3 ; 0 % ;
|
; Impedance control blocks ; 0 / 3 ; 0 % ;
|
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
|
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
|
; Average interconnect usage (total/H/V) ; 3.7% / 3.7% / 3.6% ; ;
|
; Average interconnect usage (total/H/V) ; 4.9% / 5.0% / 4.6% ; ;
|
; Peak interconnect usage (total/H/V) ; 18.4% / 18.6% / 18.7% ; ;
|
; Peak interconnect usage (total/H/V) ; 19.3% / 19.7% / 19.5% ; ;
|
; Maximum fan-out ; 3124 ; ;
|
; Maximum fan-out ; 3124 ; ;
|
; Highest non-global fan-out ; 184 ; ;
|
; Highest non-global fan-out ; 1270 ; ;
|
; Total fan-out ; 31795 ; ;
|
; Total fan-out ; 39487 ; ;
|
; Average fan-out ; 3.71 ; ;
|
; Average fan-out ; 3.76 ; ;
|
+-------------------------------------------------------------+-----------------------+-------+
|
+-------------------------------------------------------------+-----------------------+-------+
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Fitter Partition Statistics ;
|
; Fitter Partition Statistics ;
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
; Statistic ; Top ; ulight_fifo_hps_0_hps_io_border:border ; hard_block:auto_generated_inst ;
|
; Statistic ; Top ; ulight_fifo_hps_0_hps_io_border:border ; hard_block:auto_generated_inst ;
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
; Logic utilization (ALMs needed / total ALMs on device) ; 2724 / 15880 ( 17 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; Logic utilization (ALMs needed / total ALMs on device) ; 3209 / 15880 ( 20 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; ALMs needed [=A-B+C] ; 2724 ; 0 ; 0 ;
|
; ALMs needed [=A-B+C] ; 3209 ; 0 ; 0 ;
|
; [A] ALMs used in final placement [=a+b+c+d] ; 2988 / 15880 ( 19 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [A] ALMs used in final placement [=a+b+c+d] ; 3800 / 15880 ( 24 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [a] ALMs used for LUT logic and registers ; 1492 ; 0 ; 0 ;
|
; [a] ALMs used for LUT logic and registers ; 1607 ; 0 ; 0 ;
|
; [b] ALMs used for LUT logic ; 1197 ; 0 ; 0 ;
|
; [b] ALMs used for LUT logic ; 1468 ; 0 ; 0 ;
|
; [c] ALMs used for registers ; 299 ; 0 ; 0 ;
|
; [c] ALMs used for registers ; 725 ; 0 ; 0 ;
|
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; 0 ;
|
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; 0 ;
|
; [B] Estimate of ALMs recoverable by dense packing ; 270 / 15880 ( 2 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [B] Estimate of ALMs recoverable by dense packing ; 601 / 15880 ( 4 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 6 / 15880 ( < 1 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 10 / 15880 ( < 1 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [a] Due to location constrained logic ; 0 ; 0 ; 0 ;
|
; [a] Due to location constrained logic ; 0 ; 0 ; 0 ;
|
; [b] Due to LAB-wide signal conflicts ; 2 ; 0 ; 0 ;
|
; [b] Due to LAB-wide signal conflicts ; 5 ; 0 ; 0 ;
|
; [c] Due to LAB input limits ; 4 ; 0 ; 0 ;
|
; [c] Due to LAB input limits ; 5 ; 0 ; 0 ;
|
; [d] Due to virtual I/Os ; 0 ; 0 ; 0 ;
|
; [d] Due to virtual I/Os ; 0 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Difficulty packing design ; Low ; Low ; Low ;
|
; Difficulty packing design ; Low ; Low ; Low ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Total LABs: partially or completely used ; 346 / 1588 ( 22 % ) ; 0 / 1588 ( 0 % ) ; 0 / 1588 ( 0 % ) ;
|
; Total LABs: partially or completely used ; 455 / 1588 ( 29 % ) ; 0 / 1588 ( 0 % ) ; 0 / 1588 ( 0 % ) ;
|
; -- Logic LABs ; 346 ; 0 ; 0 ;
|
; -- Logic LABs ; 455 ; 0 ; 0 ;
|
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; 0 ;
|
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Combinational ALUT usage for logic ; 4775 ; 0 ; 0 ;
|
; Combinational ALUT usage for logic ; 5301 ; 0 ; 0 ;
|
; -- 7 input functions ; 57 ; 0 ; 0 ;
|
; -- 7 input functions ; 59 ; 0 ; 0 ;
|
; -- 6 input functions ; 743 ; 0 ; 0 ;
|
; -- 6 input functions ; 1198 ; 0 ; 0 ;
|
; -- 5 input functions ; 834 ; 0 ; 0 ;
|
; -- 5 input functions ; 825 ; 0 ; 0 ;
|
; -- 4 input functions ; 1357 ; 0 ; 0 ;
|
; -- 4 input functions ; 1419 ; 0 ; 0 ;
|
; -- <=3 input functions ; 1784 ; 0 ; 0 ;
|
; -- <=3 input functions ; 1800 ; 0 ; 0 ;
|
; Combinational ALUT usage for route-throughs ; 136 ; 0 ; 0 ;
|
; Combinational ALUT usage for route-throughs ; 473 ; 0 ; 0 ;
|
; Memory ALUT usage ; 0 ; 0 ; 0 ;
|
; Memory ALUT usage ; 0 ; 0 ; 0 ;
|
; -- 64-address deep ; 0 ; 0 ; 0 ;
|
; -- 64-address deep ; 0 ; 0 ; 0 ;
|
; -- 32-address deep ; 0 ; 0 ; 0 ;
|
; -- 32-address deep ; 0 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Dedicated logic registers ; 0 ; 0 ; 0 ;
|
; Dedicated logic registers ; 0 ; 0 ; 0 ;
|
; -- By type: ; ; ; ;
|
; -- By type: ; ; ; ;
|
; -- Primary logic registers ; 3581 / 31760 ( 11 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;
|
; -- Primary logic registers ; 4664 / 31760 ( 15 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;
|
; -- Secondary logic registers ; 22 / 31760 ( < 1 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;
|
; -- Secondary logic registers ; 28 / 31760 ( < 1 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;
|
; -- By function: ; ; ; ;
|
; -- By function: ; ; ; ;
|
; -- Design implementation registers ; 3603 ; 0 ; 0 ;
|
; -- Design implementation registers ; 4692 ; 0 ; 0 ;
|
; -- Routing optimization registers ; 0 ; 0 ; 0 ;
|
; -- Routing optimization registers ; 0 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Virtual pins ; 0 ; 0 ; 0 ;
|
; Virtual pins ; 0 ; 0 ; 0 ;
|
; I/O pins ; 17 ; 0 ; 2 ;
|
; I/O pins ; 17 ; 0 ; 2 ;
|
; I/O registers ; 0 ; 0 ; 0 ;
|
; I/O registers ; 0 ; 0 ; 0 ;
|
; Total block memory bits ; 1152 ; 0 ; 0 ;
|
; Total block memory bits ; 0 ; 0 ; 0 ;
|
; Total block memory implementation bits ; 20480 ; 0 ; 0 ;
|
; Total block memory implementation bits ; 0 ; 0 ; 0 ;
|
; M10K block ; 2 / 270 ( < 1 % ) ; 0 / 270 ( 0 % ) ; 0 / 270 ( 0 % ) ;
|
|
; Clock enable block ; 1 / 110 ( < 1 % ) ; 0 / 110 ( 0 % ) ; 3 / 110 ( 2 % ) ;
|
; Clock enable block ; 1 / 110 ( < 1 % ) ; 0 / 110 ( 0 % ) ; 3 / 110 ( 2 % ) ;
|
; HPS DBG APB interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; HPS DBG APB interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; Fractional PLL ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; Fractional PLL ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; HPS boot from FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; HPS boot from FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; HPS clock resets interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; HPS clock resets interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
| Line 394... |
Line 393... |
; PLL Output Counter ; 0 / 45 ( 0 % ) ; 0 / 45 ( 0 % ) ; 1 / 45 ( 2 % ) ;
|
; PLL Output Counter ; 0 / 45 ( 0 % ) ; 0 / 45 ( 0 % ) ; 1 / 45 ( 2 % ) ;
|
; PLL Reconfiguration Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; PLL Reconfiguration Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; PLL Reference Clock Select Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; PLL Reference Clock Select Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Connections ; ; ; ;
|
; Connections ; ; ; ;
|
; -- Input Connections ; 4321 ; 0 ; 45 ;
|
; -- Input Connections ; 4319 ; 0 ; 45 ;
|
; -- Registered Input Connections ; 3150 ; 0 ; 0 ;
|
; -- Registered Input Connections ; 3150 ; 0 ; 0 ;
|
; -- Output Connections ; 45 ; 0 ; 4321 ;
|
; -- Output Connections ; 45 ; 0 ; 4319 ;
|
; -- Registered Output Connections ; 1 ; 0 ; 0 ;
|
; -- Registered Output Connections ; 1 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Internal Connections ; ; ; ;
|
; Internal Connections ; ; ; ;
|
; -- Total Connections ; 32177 ; 0 ; 4403 ;
|
; -- Total Connections ; 39862 ; 0 ; 4401 ;
|
; -- Registered Connections ; 15395 ; 0 ; 0 ;
|
; -- Registered Connections ; 19902 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; External Connections ; ; ; ;
|
; External Connections ; ; ; ;
|
; -- Top ; 0 ; 0 ; 4366 ;
|
; -- Top ; 0 ; 0 ; 4364 ;
|
; -- ulight_fifo_hps_0_hps_io_border:border ; 0 ; 0 ; 0 ;
|
; -- ulight_fifo_hps_0_hps_io_border:border ; 0 ; 0 ; 0 ;
|
; -- hard_block:auto_generated_inst ; 4366 ; 0 ; 0 ;
|
; -- hard_block:auto_generated_inst ; 4364 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Partition Interface ; ; ; ;
|
; Partition Interface ; ; ; ;
|
; -- Input Ports ; 5 ; 0 ; 46 ;
|
; -- Input Ports ; 5 ; 0 ; 46 ;
|
; -- Output Ports ; 10 ; 0 ; 106 ;
|
; -- Output Ports ; 10 ; 0 ; 106 ;
|
; -- Bidir Ports ; 0 ; 0 ; 0 ;
|
; -- Bidir Ports ; 0 ; 0 ; 0 ;
|
| Line 1218... |
Line 1217... |
; -- CLKIN(2) source ; N/A ;
|
; -- CLKIN(2) source ; N/A ;
|
; -- CLKIN(3) source ; N/A ;
|
; -- CLKIN(3) source ; N/A ;
|
; -- PLL Output Counter ; ;
|
; -- PLL Output Counter ; ;
|
; -- ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[0].output_counter ; ;
|
; -- ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[0].output_counter ; ;
|
; -- Output Clock Frequency ; 400.0 MHz ;
|
; -- Output Clock Frequency ; 400.0 MHz ;
|
; -- Output Clock Location ; PLLOUTPUTCOUNTER_X68_Y2_N1 ;
|
; -- Output Clock Location ; PLLOUTPUTCOUNTER_X68_Y3_N1 ;
|
; -- C Counter Odd Divider Even Duty Enable ; Off ;
|
; -- C Counter Odd Divider Even Duty Enable ; Off ;
|
; -- Duty Cycle ; 50.0000 ;
|
; -- Duty Cycle ; 50.0000 ;
|
; -- Phase Shift ; 0.000000 degrees ;
|
; -- Phase Shift ; 0.000000 degrees ;
|
; -- C Counter ; 1 ;
|
; -- C Counter ; 1 ;
|
; -- C Counter PH Mux PRST ; 0 ;
|
; -- C Counter PH Mux PRST ; 0 ;
|
| Line 1234... |
Line 1233... |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Fitter Resource Utilization by Entity ;
|
; Fitter Resource Utilization by Entity ;
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
; |SPW_ULIGHT_FIFO ; 2723.5 (0.5) ; 2987.0 (0.5) ; 269.5 (0.0) ; 6.0 (0.0) ; 0.0 (0.0) ; 4775 (1) ; 3603 (0) ; 0 (0) ; 1152 ; 2 ; 0 ; 19 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ;
|
; |SPW_ULIGHT_FIFO ; 3209.0 (0.5) ; 3800.0 (0.5) ; 601.0 (0.0) ; 10.0 (0.0) ; 0.0 (0.0) ; 5301 (1) ; 4692 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 19 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ;
|
; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 44.7 (44.7) ; 45.5 (45.5) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 76 (76) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ;
|
; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 44.5 (44.5) ; 46.3 (46.3) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 76 (76) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ;
|
; |debounce_db:db_system_spwulight_b| ; 19.0 (19.0) ; 19.0 (19.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 38 (38) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ;
|
; |debounce_db:db_system_spwulight_b| ; 19.0 (19.0) ; 19.0 (19.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 38 (38) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ;
|
; |detector_tokens:m_x| ; 40.0 (40.0) ; 68.5 (68.5) ; 28.5 (28.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 66 (66) ; 106 (106) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ;
|
; |detector_tokens:m_x| ; 35.7 (35.7) ; 67.8 (67.8) ; 32.2 (32.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 106 (106) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ;
|
; |spw_ulight_con_top_x:A_SPW_TOP| ; 281.1 (0.3) ; 336.5 (0.3) ; 55.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 456 (1) ; 350 (0) ; 0 (0) ; 1152 ; 2 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ;
|
; |spw_ulight_con_top_x:A_SPW_TOP| ; 764.9 (0.3) ; 1126.5 (0.5) ; 365.1 (0.2) ; 3.5 (0.0) ; 0.0 (0.0) ; 984 (1) ; 1439 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ;
|
; |fifo_rx:rx_data| ; 38.1 (38.1) ; 47.7 (47.7) ; 9.6 (9.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (64) ; 71 (71) ; 0 (0) ; 576 ; 1 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ;
|
; |fifo_rx:rx_data| ; 272.4 (272.4) ; 435.3 (435.3) ; 164.4 (164.4) ; 1.5 (1.5) ; 0.0 (0.0) ; 318 (318) ; 615 (615) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ;
|
; |altsyncram:mem_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 576 ; 1 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|altsyncram:mem_rtl_0 ; altsyncram ; work ;
|
; |fifo_tx:tx_data| ; 256.6 (256.6) ; 417.8 (417.8) ; 163.3 (163.3) ; 2.0 (2.0) ; 0.0 (0.0) ; 297 (297) ; 608 (608) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ;
|
; |altsyncram_pfo1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 576 ; 1 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|altsyncram:mem_rtl_0|altsyncram_pfo1:auto_generated ; altsyncram_pfo1 ; work ;
|
; |top_spw_ultra_light:SPW| ; 235.6 (0.0) ; 272.8 (0.0) ; 37.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 368 (0) ; 216 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ;
|
; |fifo_tx:tx_data| ; 32.7 (32.7) ; 37.8 (37.8) ; 5.1 (5.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (52) ; 64 (64) ; 0 (0) ; 576 ; 1 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ;
|
; |FSM_SPW:FSM| ; 70.3 (70.3) ; 73.4 (73.4) ; 3.1 (3.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 125 (125) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ;
|
; |altsyncram:mem_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 576 ; 1 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|altsyncram:mem_rtl_0 ; altsyncram ; work ;
|
; |RX_SPW:RX| ; 41.9 (41.9) ; 64.4 (64.4) ; 22.5 (22.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 68 (68) ; 109 (109) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ;
|
; |altsyncram_pfo1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 576 ; 1 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|altsyncram:mem_rtl_0|altsyncram_pfo1:auto_generated ; altsyncram_pfo1 ; work ;
|
; |TX_SPW:TX| ; 123.3 (123.3) ; 135.0 (135.0) ; 11.7 (11.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 175 (175) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ;
|
; |top_spw_ultra_light:SPW| ; 209.8 (0.0) ; 250.7 (0.0) ; 40.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 339 (0) ; 215 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ;
|
; |ulight_fifo:u0| ; 2344.4 (0.0) ; 2539.8 (0.0) ; 201.9 (0.0) ; 6.5 (0.0) ; 0.0 (0.0) ; 4143 (0) ; 3105 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ;
|
; |FSM_SPW:FSM| ; 66.7 (66.7) ; 75.8 (75.8) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 119 (119) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ;
|
|
; |RX_SPW:RX| ; 42.0 (42.0) ; 64.7 (64.7) ; 22.7 (22.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 66 (66) ; 109 (109) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ;
|
|
; |TX_SPW:TX| ; 101.2 (101.2) ; 110.3 (110.3) ; 9.1 (9.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 154 (154) ; 59 (59) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ;
|
|
; |ulight_fifo:u0| ; 2338.2 (0.0) ; 2517.0 (0.0) ; 184.7 (0.0) ; 6.0 (0.0) ; 0.0 (0.0) ; 4138 (0) ; 3105 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ;
|
|
; |altera_reset_controller:rst_controller| ; 0.0 (0.0) ; 1.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; altera_reset_controller ; ulight_fifo ;
|
; |altera_reset_controller:rst_controller| ; 0.0 (0.0) ; 1.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; altera_reset_controller ; ulight_fifo ;
|
; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;
|
; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;
|
; |altera_reset_controller:rst_controller_001| ; 0.7 (0.0) ; 1.5 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; ulight_fifo ;
|
; |altera_reset_controller:rst_controller_001| ; 0.7 (0.0) ; 1.3 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; ulight_fifo ;
|
; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.7 (0.7) ; 1.5 (1.5) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;
|
; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.7 (0.7) ; 1.3 (1.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;
|
; |ulight_fifo_auto_start:auto_start| ; 0.6 (0.6) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:auto_start| ; 0.7 (0.7) ; 1.0 (1.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:data_read_en_rx| ; 1.2 (1.2) ; 1.7 (1.7) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:data_read_en_rx| ; 0.9 (0.9) ; 1.1 (1.1) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:link_disable| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:link_disable| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:link_start| ; 0.9 (0.9) ; 1.1 (1.1) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:link_start| ; 0.9 (0.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:timecode_tx_enable| ; 1.0 (1.0) ; 1.2 (1.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:timecode_tx_enable| ; 1.0 (1.0) ; 1.1 (1.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:write_en_tx| ; 0.8 (0.8) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_auto_start:write_en_tx| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo_auto_start ; ulight_fifo ;
|
; |ulight_fifo_clock_sel:clock_sel| ; 2.1 (2.1) ; 2.3 (2.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo_clock_sel ; ulight_fifo ;
|
; |ulight_fifo_clock_sel:clock_sel| ; 2.1 (2.1) ; 2.6 (2.6) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo_clock_sel ; ulight_fifo ;
|
; |ulight_fifo_counter_rx_fifo:counter_rx_fifo| ; 3.0 (3.0) ; 3.1 (3.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
; |ulight_fifo_counter_rx_fifo:counter_rx_fifo| ; 3.0 (3.0) ; 3.1 (3.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
; |ulight_fifo_counter_rx_fifo:counter_tx_fifo| ; 3.0 (3.0) ; 3.2 (3.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
; |ulight_fifo_counter_rx_fifo:counter_tx_fifo| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
; |ulight_fifo_counter_rx_fifo:fsm_info| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
; |ulight_fifo_counter_rx_fifo:fsm_info| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
; |ulight_fifo_data_flag_rx:data_flag_rx| ; 4.7 (4.7) ; 4.7 (4.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo_data_flag_rx ; ulight_fifo ;
|
; |ulight_fifo_data_flag_rx:data_flag_rx| ; 5.2 (5.2) ; 5.2 (5.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo_data_flag_rx ; ulight_fifo ;
|
; |ulight_fifo_data_info:data_info| ; 7.0 (7.0) ; 7.1 (7.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ;
|
; |ulight_fifo_data_info:data_info| ; 7.1 (7.1) ; 7.1 (7.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:timecode_ready_rx| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:timecode_ready_rx| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:timecode_tx_ready| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:timecode_tx_ready| ; 0.4 (0.4) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_hps_0:hps_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo_hps_0 ; ulight_fifo ;
|
; |ulight_fifo_hps_0:hps_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo_hps_0 ; ulight_fifo ;
|
; |ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces ; ulight_fifo_hps_0_fpga_interfaces ; ulight_fifo ;
|
; |ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces ; ulight_fifo_hps_0_fpga_interfaces ; ulight_fifo ;
|
; |ulight_fifo_led_pio_test:led_pio_test| ; 2.3 (2.3) ; 3.9 (3.9) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo_led_pio_test ; ulight_fifo ;
|
; |ulight_fifo_led_pio_test:led_pio_test| ; 2.2 (2.2) ; 3.9 (3.9) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo_led_pio_test ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 2292.8 (0.0) ; 2459.8 (0.0) ; 173.0 (0.0) ; 6.0 (0.0) ; 0.0 (0.0) ; 4041 (0) ; 3014 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 2300.2 (0.0) ; 2484.3 (0.0) ; 190.6 (0.0) ; 6.5 (0.0) ; 0.0 (0.0) ; 4046 (0) ; 3014 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo| ; 3.4 (3.4) ; 3.3 (3.3) ; 0.1 (0.1) ; 0.2 (0.2) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo| ; 17.8 (17.8) ; 20.5 (20.5) ; 3.0 (3.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo| ; 18.6 (18.6) ; 21.8 (21.8) ; 3.3 (3.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo| ; 3.8 (3.8) ; 3.8 (3.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo| ; 4.5 (4.5) ; 4.8 (4.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo| ; 19.3 (19.3) ; 20.8 (20.8) ; 1.8 (1.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo| ; 18.9 (18.9) ; 20.0 (20.0) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo| ; 5.8 (5.8) ; 5.8 (5.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo| ; 5.4 (5.4) ; 5.4 (5.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo| ; 14.1 (14.1) ; 21.2 (21.2) ; 7.1 (7.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo| ; 14.3 (14.3) ; 21.0 (21.0) ; 6.8 (6.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo| ; 5.5 (5.5) ; 5.5 (5.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo| ; 6.0 (6.0) ; 6.0 (6.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo| ; 16.9 (16.9) ; 18.2 (18.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo| ; 17.5 (17.5) ; 17.1 (17.1) ; 0.0 (0.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo| ; 8.3 (8.3) ; 8.3 (8.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo| ; 8.9 (8.9) ; 8.9 (8.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo| ; 19.4 (19.4) ; 19.1 (19.1) ; 0.2 (0.2) ; 0.5 (0.5) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo| ; 19.3 (19.3) ; 19.2 (19.2) ; 0.0 (0.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 13.3 (13.3) ; 13.3 (13.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 19 (19) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 13.7 (13.7) ; 13.8 (13.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 19 (19) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo| ; 15.8 (15.8) ; 19.2 (19.2) ; 3.8 (3.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo| ; 14.0 (14.0) ; 21.8 (21.8) ; 7.8 (7.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo| ; 19.2 (19.2) ; 19.5 (19.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo| ; 19.4 (19.4) ; 20.3 (20.3) ; 1.3 (1.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo| ; 17.2 (17.2) ; 19.1 (19.1) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo| ; 17.1 (17.1) ; 17.9 (17.9) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo| ; 2.5 (2.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo| ; 2.4 (2.4) ; 2.8 (2.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo| ; 17.8 (17.8) ; 18.3 (18.3) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo| ; 17.6 (17.6) ; 17.6 (17.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo| ; 17.8 (17.8) ; 17.8 (17.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo| ; 18.2 (18.2) ; 18.6 (18.6) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.5 (3.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo| ; 14.1 (14.1) ; 20.2 (20.2) ; 6.1 (6.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo| ; 14.3 (14.3) ; 19.0 (19.0) ; 4.7 (4.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo| ; 5.6 (5.6) ; 5.6 (5.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo| ; 5.5 (5.5) ; 5.5 (5.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo| ; 16.9 (16.9) ; 16.9 (16.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo| ; 17.8 (17.8) ; 17.8 (17.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo| ; 6.0 (6.0) ; 6.2 (6.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo| ; 5.7 (5.7) ; 5.7 (5.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo| ; 18.0 (18.0) ; 21.7 (21.7) ; 3.7 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo| ; 16.6 (16.6) ; 23.4 (23.4) ; 6.8 (6.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 3.0 (3.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo| ; 19.4 (19.4) ; 21.3 (21.3) ; 2.4 (2.4) ; 0.5 (0.5) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo| ; 20.1 (20.1) ; 21.0 (21.0) ; 1.9 (1.9) ; 1.0 (1.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo| ; 3.1 (3.1) ; 3.1 (3.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo| ; 16.5 (16.5) ; 22.1 (22.1) ; 5.6 (5.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo| ; 16.2 (16.2) ; 23.3 (23.3) ; 7.0 (7.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo| ; 2.5 (2.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 3.3 (3.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo| ; 17.5 (17.5) ; 17.9 (17.9) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo| ; 17.5 (17.5) ; 17.7 (17.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo| ; 7.8 (7.8) ; 8.2 (8.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo| ; 6.9 (6.9) ; 6.9 (6.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo| ; 18.6 (18.6) ; 19.5 (19.5) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo| ; 17.9 (17.9) ; 18.8 (18.8) ; 0.9 (0.9) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 7.8 (7.8) ; 9.1 (9.1) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 7.0 (7.0) ; 7.0 (7.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo| ; 18.9 (18.9) ; 20.4 (20.4) ; 1.6 (1.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo| ; 18.8 (18.8) ; 20.3 (20.3) ; 1.8 (1.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 3.0 (3.0) ; 3.1 (3.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 2.9 (2.9) ; 3.1 (3.1) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo| ; 19.0 (19.0) ; 19.5 (19.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo| ; 18.2 (18.2) ; 20.1 (20.1) ; 1.9 (1.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo| ; 17.6 (17.6) ; 18.7 (18.7) ; 1.7 (1.7) ; 0.5 (0.5) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo| ; 17.3 (17.3) ; 18.3 (18.3) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 9.7 (9.7) ; 9.8 (9.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 8.3 (8.3) ; 8.3 (8.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo| ; 18.3 (18.3) ; 19.2 (19.2) ; 1.3 (1.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo| ; 20.0 (20.0) ; 20.5 (20.5) ; 1.3 (1.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 3.0 (3.0) ; 3.1 (3.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 3.2 (3.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo| ; 19.3 (19.3) ; 20.8 (20.8) ; 1.6 (1.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo| ; 19.4 (19.4) ; 20.5 (20.5) ; 1.2 (1.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 60.9 (29.1) ; 60.9 (29.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 116 (57) ; 26 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ;
|
; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 62.2 (28.7) ; 62.2 (30.7) ; 0.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 114 (55) ; 26 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 31.8 (31.8) ; 31.8 (31.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 31.5 (31.5) ; 31.5 (31.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 43.2 (0.0) ; 45.5 (0.0) ; 2.3 (0.0) ; 0.1 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 42.4 (0.0) ; 45.2 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.2 (43.0) ; 45.5 (45.2) ; 2.3 (2.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.4 (42.2) ; 45.2 (44.9) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 43.5 (0.0) ; 46.3 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 44.2 (0.0) ; 46.7 (0.0) ; 2.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.5 (43.3) ; 46.3 (46.1) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.2 (44.0) ; 46.7 (46.4) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 38.4 (0.0) ; 40.4 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 38.8 (0.0) ; 41.3 (0.0) ; 2.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.4 (37.8) ; 40.4 (39.7) ; 2.0 (1.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.8 (37.8) ; 41.3 (40.8) ; 2.5 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 38.3 (0.0) ; 40.4 (0.0) ; 2.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 38.3 (0.0) ; 42.0 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.3 (37.6) ; 40.4 (39.6) ; 2.1 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.3 (37.6) ; 42.0 (41.7) ; 3.7 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 37.2 (0.0) ; 39.4 (0.0) ; 2.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 35.4 (0.0) ; 38.3 (0.0) ; 2.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 37.2 (36.4) ; 39.4 (38.8) ; 2.2 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 35.4 (34.8) ; 38.3 (37.3) ; 2.9 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 1.0 (1.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 36.9 (0.0) ; 40.1 (0.0) ; 3.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 36.0 (0.0) ; 38.8 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.9 (36.0) ; 40.1 (39.5) ; 3.2 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.0 (35.3) ; 38.8 (38.3) ; 2.8 (2.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 43.2 (0.0) ; 44.8 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 42.5 (0.0) ; 45.1 (0.0) ; 2.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.2 (42.9) ; 44.8 (44.5) ; 1.5 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.5 (42.2) ; 45.1 (44.6) ; 2.6 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 36.9 (0.0) ; 38.2 (0.0) ; 1.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 36.8 (0.0) ; 38.4 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.9 (36.3) ; 38.2 (37.6) ; 1.2 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.8 (36.1) ; 38.4 (38.1) ; 1.7 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 37.1 (0.0) ; 38.7 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 36.3 (0.0) ; 38.2 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 37.1 (36.3) ; 38.7 (38.1) ; 1.6 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.3 (35.9) ; 38.2 (37.9) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (51) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 36.0 (0.0) ; 39.1 (0.0) ; 3.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 36.7 (0.0) ; 39.8 (0.0) ; 3.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.0 (35.7) ; 39.1 (38.8) ; 3.1 (3.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (51) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.7 (36.4) ; 39.8 (39.8) ; 3.0 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (51) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 39.9 (0.0) ; 40.2 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 39.0 (0.0) ; 42.6 (0.0) ; 3.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.9 (38.9) ; 40.2 (39.6) ; 0.3 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.0 (38.3) ; 42.6 (41.9) ; 3.6 (3.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 38.1 (0.0) ; 40.0 (0.0) ; 1.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 55 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 37.9 (0.0) ; 41.7 (0.0) ; 3.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 55 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.1 (37.4) ; 40.0 (39.4) ; 1.9 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 55 (53) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 37.9 (37.6) ; 41.7 (41.2) ; 3.8 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 55 (54) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 45.2 (0.0) ; 46.8 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (0) ; 66 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 47.4 (0.0) ; 51.8 (0.0) ; 4.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (0) ; 66 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.2 (45.0) ; 46.8 (46.6) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (66) ; 66 (66) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 47.4 (47.2) ; 51.8 (51.6) ; 4.4 (4.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (66) ; 66 (66) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 43.4 (0.0) ; 46.2 (0.0) ; 3.1 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 42.4 (0.0) ; 45.3 (0.0) ; 2.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.4 (43.1) ; 46.2 (45.9) ; 3.1 (3.1) ; 0.3 (0.3) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.4 (42.2) ; 45.3 (45.1) ; 2.9 (2.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 42.9 (0.0) ; 44.7 (0.0) ; 1.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 42.3 (0.0) ; 45.6 (0.0) ; 3.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.9 (42.7) ; 44.7 (44.5) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.3 (42.1) ; 45.6 (45.3) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 37.5 (0.0) ; 44.5 (0.0) ; 7.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 56 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 36.7 (0.0) ; 41.1 (0.0) ; 4.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 37.5 (36.2) ; 44.5 (43.5) ; 7.0 (7.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 56 (54) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.7 (36.0) ; 41.1 (40.2) ; 4.4 (4.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 37.9 (0.0) ; 38.5 (0.0) ; 0.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 56 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 36.8 (0.0) ; 39.4 (0.0) ; 2.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 37.9 (37.6) ; 38.5 (38.5) ; 0.6 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 56 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.8 (36.4) ; 39.4 (39.4) ; 2.7 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (51) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 45.3 (0.0) ; 48.0 (0.0) ; 2.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 69 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 45.6 (0.0) ; 49.7 (0.0) ; 4.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 69 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.3 (45.1) ; 48.0 (47.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 69 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.6 (45.3) ; 49.7 (49.4) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 69 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 44.0 (0.0) ; 45.7 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 43.0 (0.0) ; 45.4 (0.0) ; 2.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.0 (43.7) ; 45.7 (45.4) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.0 (42.7) ; 45.4 (45.4) ; 2.4 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 36.1 (0.0) ; 39.7 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 36.3 (0.0) ; 39.9 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.1 (35.4) ; 39.7 (38.9) ; 3.7 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.3 (35.4) ; 39.9 (39.3) ; 3.7 (3.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 44.0 (0.0) ; 46.2 (0.0) ; 2.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 70 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 44.8 (0.0) ; 47.1 (0.0) ; 2.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 70 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.0 (43.7) ; 46.2 (45.9) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 70 (70) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.8 (44.6) ; 47.1 (46.8) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 70 (70) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 42.5 (0.0) ; 43.7 (0.0) ; 1.3 (0.0) ; 0.2 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 42.2 (0.0) ; 46.2 (0.0) ; 4.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.5 (42.2) ; 43.7 (43.4) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.2 (41.9) ; 46.2 (45.9) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
; |altera_merlin_slave_agent:auto_start_s1_agent| ; 16.3 (6.3) ; 16.2 (6.5) ; 0.0 (0.2) ; 0.2 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:auto_start_s1_agent| ; 16.2 (5.8) ; 16.7 (6.1) ; 0.5 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.4 (10.4) ; 10.6 (10.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:clock_sel_s1_agent| ; 14.8 (5.6) ; 14.8 (5.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:clock_sel_s1_agent| ; 15.7 (5.8) ; 16.3 (6.3) ; 0.7 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 12.2 (2.2) ; 12.3 (2.5) ; 0.1 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 12.3 (2.2) ; 12.3 (2.7) ; 0.0 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 11.3 (2.2) ; 11.3 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 12.1 (2.2) ; 12.1 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 11.9 (2.6) ; 12.5 (2.8) ; 0.6 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 12.3 (2.3) ; 12.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.7 (9.7) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.0 (10.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:data_info_s1_agent| ; 12.6 (2.5) ; 13.7 (2.8) ; 1.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:data_info_s1_agent| ; 12.5 (2.6) ; 12.5 (2.8) ; 0.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.9 (10.9) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 15.0 (5.2) ; 15.0 (5.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 15.1 (5.7) ; 15.1 (5.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 12.2 (2.2) ; 12.2 (3.2) ; 0.0 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 11.8 (2.3) ; 11.8 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.0 (9.0) ; 9.0 (9.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 12.2 (2.2) ; 12.2 (2.8) ; 0.0 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 12.4 (2.2) ; 12.8 (3.3) ; 0.4 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:fifo_full_rx_status_s1_agent| ; 12.1 (2.3) ; 12.1 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:fifo_full_rx_status_s1_agent| ; 11.7 (2.5) ; 11.7 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:fifo_full_tx_status_s1_agent| ; 12.3 (2.4) ; 12.3 (2.8) ; 0.0 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:fifo_full_tx_status_s1_agent| ; 11.9 (2.4) ; 11.9 (2.5) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 12.2 (2.4) ; 12.2 (2.8) ; 0.0 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 12.2 (2.9) ; 12.2 (2.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.3 (9.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 15.7 (6.2) ; 17.0 (6.7) ; 1.3 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 14.9 (5.5) ; 14.9 (5.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 10.3 (10.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:link_disable_s1_agent| ; 15.9 (6.1) ; 16.1 (6.1) ; 0.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:link_disable_s1_agent| ; 16.1 (5.6) ; 16.5 (5.6) ; 0.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.9 (10.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:link_start_s1_agent| ; 15.2 (5.8) ; 15.2 (5.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:link_start_s1_agent| ; 15.6 (5.3) ; 15.6 (5.7) ; 0.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.9 (9.9) ; 9.9 (9.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_ready_rx_s1_agent| ; 11.8 (2.4) ; 11.8 (2.7) ; 0.0 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_ready_rx_s1_agent| ; 12.6 (2.5) ; 12.6 (2.8) ; 0.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 11.5 (2.2) ; 11.5 (2.5) ; 0.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 12.8 (2.6) ; 13.2 (3.1) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.0 (9.0) ; 9.0 (9.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.2 (10.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 15.7 (6.2) ; 15.7 (6.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 16.5 (6.3) ; 17.6 (6.3) ; 1.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 11.2 (11.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 14.8 (5.5) ; 15.4 (5.9) ; 0.6 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 16.0 (5.7) ; 16.2 (5.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.5 (9.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.3 (10.3) ; 10.3 (10.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 12.5 (2.6) ; 12.5 (3.0) ; 0.0 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 12.7 (2.2) ; 13.2 (2.7) ; 0.6 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.5 (10.5) ; 10.6 (10.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 15.3 (5.7) ; 15.3 (6.1) ; 0.0 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 15.8 (5.4) ; 15.8 (6.0) ; 0.0 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 15.6 (5.6) ; 16.3 (5.7) ; 0.7 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 15.0 (5.9) ; 15.0 (5.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.7 (10.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.1 (9.1) ; 9.1 (9.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_translator:auto_start_s1_translator| ; 2.6 (2.6) ; 4.0 (4.0) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:auto_start_s1_translator| ; 2.3 (2.3) ; 3.3 (3.3) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:clock_sel_s1_translator| ; 2.7 (2.7) ; 3.8 (3.8) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:clock_sel_s1_translator| ; 2.7 (2.7) ; 3.7 (3.7) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 2.1 (2.1) ; 4.0 (4.0) ; 1.9 (1.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 1.5 (1.5) ; 4.1 (4.1) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 3.0 (3.0) ; 4.6 (4.6) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 2.2 (2.2) ; 4.1 (4.1) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 2.3 (2.3) ; 4.8 (4.8) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 1.2 (1.2) ; 4.8 (4.8) ; 3.6 (3.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_info_s1_translator| ; 1.3 (1.3) ; 5.9 (5.9) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_info_s1_translator| ; 1.7 (1.7) ; 6.3 (6.3) ; 4.6 (4.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_read_en_rx_s1_translator| ; 2.2 (2.2) ; 3.2 (3.2) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_read_en_rx_s1_translator| ; 2.4 (2.4) ; 3.1 (3.1) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 2.1 (2.1) ; 2.2 (2.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 2.2 (2.2) ; 3.2 (3.2) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 2.1 (2.1) ; 3.0 (3.0) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 2.1 (2.1) ; 3.2 (3.2) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 1.5 (1.5) ; 3.2 (3.2) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 1.6 (1.6) ; 3.0 (3.0) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 1.8 (1.8) ; 3.7 (3.7) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 1.8 (1.8) ; 3.7 (3.7) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:led_pio_test_s1_translator| ; 3.3 (3.3) ; 4.6 (4.6) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:led_pio_test_s1_translator| ; 3.8 (3.8) ; 3.7 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:link_disable_s1_translator| ; 2.3 (2.3) ; 3.2 (3.2) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:link_disable_s1_translator| ; 2.4 (2.4) ; 3.2 (3.2) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:link_start_s1_translator| ; 2.6 (2.6) ; 3.1 (3.1) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:link_start_s1_translator| ; 2.3 (2.3) ; 3.2 (3.2) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 2.1 (2.1) ; 3.2 (3.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 2.5 (2.5) ; 5.1 (5.1) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 2.8 (2.8) ; 4.2 (4.2) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_tx_data_s1_translator| ; 4.4 (4.4) ; 5.0 (5.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_tx_data_s1_translator| ; 4.2 (4.2) ; 5.0 (5.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_tx_enable_s1_translator| ; 3.2 (3.2) ; 3.4 (3.4) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_tx_enable_s1_translator| ; 2.8 (2.8) ; 3.2 (3.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 2.1 (2.1) ; 3.0 (3.0) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:write_data_fifo_tx_s1_translator| ; 4.9 (4.9) ; 5.2 (5.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:write_data_fifo_tx_s1_translator| ; 4.8 (4.8) ; 5.0 (5.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:write_en_tx_s1_translator| ; 2.8 (2.8) ; 3.2 (3.2) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:write_en_tx_s1_translator| ; 2.4 (2.4) ; 3.1 (3.1) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 14.8 (14.8) ; 14.8 (14.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;
|
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 14.5 (14.5) ; 14.5 (14.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;
|
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 13.5 (13.5) ; 13.9 (13.9) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;
|
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 12.8 (12.8) ; 13.5 (13.5) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 15.2 (15.2) ; 16.0 (16.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 15.7 (15.7) ; 17.7 (17.7) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 31 (31) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 23.8 (23.8) ; 25.3 (25.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (40) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 23.8 (23.8) ; 25.3 (25.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (40) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 12.9 (10.7) ; 12.9 (10.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (33) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 13.1 (10.8) ; 13.3 (11.2) ; 0.2 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (33) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 2.2 (2.2) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 2.1 (2.1) ; 2.1 (2.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001| ; 5.5 (5.5) ; 6.3 (6.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 18 (18) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001| ; 6.4 (6.4) ; 6.4 (6.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002| ; 6.0 (6.0) ; 7.0 (7.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 18 (18) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002| ; 6.3 (6.3) ; 7.1 (7.1) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003| ; 6.0 (6.0) ; 6.6 (6.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003| ; 6.7 (6.7) ; 7.7 (7.7) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 12.7 (10.3) ; 13.4 (10.4) ; 0.8 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 12.8 (10.2) ; 13.7 (11.1) ; 1.0 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 2.3 (2.3) ; 3.0 (3.0) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 2.6 (2.6) ; 2.7 (2.7) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005| ; 6.3 (6.3) ; 6.3 (6.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005| ; 6.1 (6.1) ; 6.2 (6.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006| ; 5.8 (5.8) ; 5.8 (5.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006| ; 6.4 (6.4) ; 6.4 (6.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 11.9 (10.3) ; 12.9 (10.9) ; 1.0 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 11.9 (10.6) ; 12.6 (10.8) ; 0.7 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 1.7 (1.7) ; 2.0 (2.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 13.8 (9.5) ; 14.8 (10.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 13.7 (9.7) ; 14.7 (10.4) ; 1.1 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 4.3 (4.3) ; 4.3 (4.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 4.0 (4.0) ; 4.3 (4.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009| ; 12.4 (9.8) ; 13.9 (10.4) ; 1.5 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009| ; 12.8 (9.5) ; 14.4 (11.1) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 2.7 (2.7) ; 3.5 (3.5) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010| ; 14.8 (11.8) ; 16.5 (12.8) ; 1.7 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (37) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010| ; 14.5 (11.6) ; 16.7 (12.7) ; 2.2 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (37) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 3.0 (3.0) ; 3.7 (3.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 2.9 (2.9) ; 4.0 (4.0) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 12.1 (10.1) ; 12.5 (10.7) ; 0.4 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 11.3 (9.3) ; 12.5 (10.7) ; 1.2 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012| ; 6.0 (6.0) ; 6.2 (6.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012| ; 6.3 (6.3) ; 6.8 (6.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013| ; 5.9 (5.9) ; 6.6 (6.6) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013| ; 6.4 (6.4) ; 6.9 (6.9) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 13.4 (11.4) ; 13.9 (11.4) ; 0.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 41 (36) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 13.8 (11.2) ; 14.8 (12.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 41 (36) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 2.5 (2.5) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 11.4 (9.4) ; 11.8 (9.5) ; 0.4 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 32 (28) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 11.7 (9.3) ; 12.3 (10.1) ; 0.7 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 32 (28) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.3 (2.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 2.2 (2.2) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 6.8 (6.8) ; 7.1 (7.1) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (23) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 6.8 (6.8) ; 7.4 (7.4) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (23) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017| ; 6.2 (6.2) ; 6.7 (6.7) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017| ; 6.7 (6.7) ; 6.7 (6.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 12.7 (9.8) ; 14.3 (10.8) ; 1.7 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (31) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 13.0 (9.7) ; 13.0 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (31) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 2.8 (2.8) ; 3.5 (3.5) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |altera_merlin_arbitrator:arb| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019| ; 6.3 (6.3) ; 6.4 (6.4) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019| ; 6.0 (6.0) ; 6.7 (6.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020| ; 4.5 (4.5) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020| ; 6.7 (6.7) ; 6.7 (6.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021| ; 6.8 (6.8) ; 7.1 (7.1) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021| ; 6.3 (6.3) ; 6.3 (6.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_router:router| ; 13.2 (13.2) ; 18.8 (18.8) ; 5.7 (5.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_router:router| ; 14.3 (14.3) ; 17.3 (17.3) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_router:router_001| ; 20.2 (20.2) ; 23.3 (23.3) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 44 (44) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_router:router_001| ; 21.0 (21.0) ; 23.5 (23.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 44 (44) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux| ; 0.9 (0.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux| ; 1.1 (1.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004| ; 1.1 (1.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007| ; 1.0 (1.0) ; 1.2 (1.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007| ; 0.9 (0.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008| ; 1.2 (1.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008| ; 1.1 (1.1) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009| ; 1.6 (1.6) ; 1.6 (1.6) ; 0.1 (0.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010| ; 1.5 (1.5) ; 1.6 (1.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011| ; 1.3 (1.3) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.1 (0.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014| ; 1.2 (1.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015| ; 1.3 (1.3) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015| ; 1.4 (1.4) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018| ; 1.2 (1.2) ; 1.7 (1.7) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018| ; 0.8 (0.8) ; 1.2 (1.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux| ; 34.3 (34.3) ; 38.2 (38.2) ; 4.1 (4.1) ; 0.2 (0.2) ; 0.0 (0.0) ; 88 (88) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux| ; 36.5 (36.5) ; 40.3 (40.3) ; 5.2 (5.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 88 (88) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 120.3 (120.3) ; 153.5 (153.5) ; 35.0 (35.0) ; 1.8 (1.8) ; 0.0 (0.0) ; 294 (294) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 128.4 (128.4) ; 156.2 (156.2) ; 29.3 (29.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 300 (300) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;
|
; |ulight_fifo_pll_0:pll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo_pll_0 ; ulight_fifo ;
|
; |ulight_fifo_pll_0:pll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo_pll_0 ; ulight_fifo ;
|
; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ; altera_pll ; work ;
|
; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ; altera_pll ; work ;
|
; |altera_cyclonev_pll:cyclonev_pll| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll ; altera_cyclonev_pll ; work ;
|
; |altera_cyclonev_pll:cyclonev_pll| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll ; altera_cyclonev_pll ; work ;
|
; |altera_cyclonev_pll_base:fpll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0 ; altera_cyclonev_pll_base ; work ;
|
; |altera_cyclonev_pll_base:fpll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0 ; altera_cyclonev_pll_base ; work ;
|
; |ulight_fifo_timecode_rx:timecode_rx| ; 4.0 (4.0) ; 4.1 (4.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo_timecode_rx ; ulight_fifo ;
|
; |ulight_fifo_timecode_rx:timecode_rx| ; 4.2 (4.2) ; 4.2 (4.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo_timecode_rx ; ulight_fifo ;
|
; |ulight_fifo_timecode_tx_data:timecode_tx_data| ; 4.3 (4.3) ; 6.2 (6.2) ; 1.9 (1.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo_timecode_tx_data ; ulight_fifo ;
|
; |ulight_fifo_timecode_tx_data:timecode_tx_data| ; 2.3 (2.3) ; 6.3 (6.3) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo_timecode_tx_data ; ulight_fifo ;
|
; |ulight_fifo_write_data_fifo_tx:write_data_fifo_tx| ; 2.6 (2.6) ; 7.1 (7.1) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo_write_data_fifo_tx ; ulight_fifo ;
|
; |ulight_fifo_write_data_fifo_tx:write_data_fifo_tx| ; 2.6 (2.6) ; 7.1 (7.1) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo_write_data_fifo_tx ; ulight_fifo ;
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
; Delay Chain Summary ;
|
; Delay Chain Summary ;
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
; LED[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
|
; LED[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
|
; dout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; dout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; sout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; sout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
|
; LED[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
|
; LED[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; KEY[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; KEY[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; LED[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; FPGA_CLK1_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; FPGA_CLK1_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; din_a ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; din_a ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; sin_a ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; sin_a ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; dout_a(n) ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; dout_a(n) ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; sout_a(n) ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; sout_a(n) ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; din_a(n) ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; din_a(n) ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; sin_a(n) ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; sin_a(n) ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------------------------------------------------------+
|
| Line 1550... |
Line 1545... |
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
+----------------------------------------------------------------------------------------------+-------------------+---------+
|
+----------------------------------------------------------------------------------------------+-------------------+---------+
|
; KEY[0] ; ; ;
|
; KEY[0] ; ; ;
|
; FPGA_CLK1_50 ; ; ;
|
; FPGA_CLK1_50 ; ; ;
|
; KEY[1] ; ; ;
|
; KEY[1] ; ; ;
|
; - debounce_db:db_system_spwulight_b|aux_pb~0 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|PB_down~0 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~0 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~0 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter[0]~1 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter[13]~1 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~2 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~2 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~3 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~3 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~4 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~4 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~5 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~5 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~6 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~6 ; 0 ; 0 ;
|
| Line 1568... |
Line 1563... |
; - debounce_db:db_system_spwulight_b|counter~12 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~12 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~13 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~13 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~14 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~14 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~15 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~15 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~16 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~16 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|PB_down~0 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|PB_down~1 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|aux_pb~1 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|aux_pb~0 ; 0 ; 0 ;
|
; din_a ; ; ;
|
; din_a ; ; ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_1 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_1 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|control_bit_found ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|control_bit_found ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_1 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_1 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~4 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~3 ; 0 ; 0 ;
|
; sin_a ; ; ;
|
; sin_a ; ; ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~3 ; 1 ; 0 ;
|
|
; din_a(n) ; ; ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_1 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_0 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|control_bit_found ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_1 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_0 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~4 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~4 ; 1 ; 0 ;
|
|
; din_a(n) ; ; ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_1 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_0 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|control_bit_found ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_1 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_0 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~3 ; 0 ; 0 ;
|
; sin_a(n) ; ; ;
|
; sin_a(n) ; ; ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~3 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~4 ; 1 ; 0 ;
|
+----------------------------------------------------------------------------------------------+-------------------+---------+
|
+----------------------------------------------------------------------------------------------+-------------------+---------+
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Control Signals ;
|
; Control Signals ;
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
; FPGA_CLK1_50 ; PIN_Y13 ; 3124 ; Clock ; yes ; Global Clock ; GCLK5 ; -- ;
|
; FPGA_CLK1_50 ; PIN_Y13 ; 3124 ; Clock ; yes ; Global Clock ; GCLK5 ; -- ;
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FF_X18_Y10_N38 ; 184 ; Clock ; no ; -- ; -- ; -- ;
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FF_X27_Y11_N29 ; 1270 ; Clock ; no ; -- ; -- ; -- ;
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FF_X30_Y10_N44 ; 59 ; Clock ; no ; -- ; -- ; -- ;
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FF_X13_Y17_N26 ; 60 ; Clock ; no ; -- ; -- ; -- ;
|
; debounce_db:db_system_spwulight_b|aux_pb ; FF_X47_Y1_N32 ; 130 ; Async. clear ; no ; -- ; -- ; -- ;
|
; debounce_db:db_system_spwulight_b|PB_down~0 ; MLABCELL_X47_Y1_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; debounce_db:db_system_spwulight_b|aux_pb~0 ; MLABCELL_X47_Y1_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; debounce_db:db_system_spwulight_b|aux_pb ; FF_X47_Y1_N14 ; 127 ; Async. clear ; no ; -- ; -- ; -- ;
|
; debounce_db:db_system_spwulight_b|counter[0]~1 ; MLABCELL_X47_Y1_N21 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
|
; debounce_db:db_system_spwulight_b|counter[13]~1 ; MLABCELL_X47_Y1_N21 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|WideOr7~0 ; LABCELL_X35_Y7_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|WideOr7~0 ; LABCELL_X18_Y14_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|always1~0 ; LABCELL_X36_Y7_N6 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|always1~0 ; LABCELL_X23_Y14_N12 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|always2~0 ; LABCELL_X36_Y7_N3 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|always2~0 ; LABCELL_X23_Y14_N48 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|always3~0 ; LABCELL_X31_Y11_N27 ; 84 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|always3~0 ; MLABCELL_X19_Y14_N21 ; 84 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|data[8]~2 ; MLABCELL_X32_Y7_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|data[8]~2 ; MLABCELL_X19_Y15_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|data_l_r[7]~0 ; LABCELL_X36_Y7_N48 ; 19 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|data_l_r[7]~0 ; MLABCELL_X19_Y15_N9 ; 19 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|data_l_r[7]~1 ; MLABCELL_X32_Y7_N15 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|data_l_r[7]~1 ; MLABCELL_X19_Y15_N21 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|is_control ; FF_X36_Y7_N38 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|is_control ; FF_X23_Y14_N56 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|ready_control_p_r ; FF_X36_Y7_N59 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|ready_control_p_r ; FF_X19_Y15_N20 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|ready_data_p ; LABCELL_X36_Y7_N12 ; 19 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|ready_data_p ; LABCELL_X23_Y14_N39 ; 19 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|rx_got_null~0 ; LABCELL_X35_Y7_N48 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|rx_got_time_code~1 ; LABCELL_X18_Y15_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|timecode[7]~0 ; MLABCELL_X32_Y7_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|timecode[7]~0 ; LABCELL_X22_Y15_N9 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always0~0 ; LABCELL_X18_Y11_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~10 ; LABCELL_X35_Y8_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always1~0 ; LABCELL_X21_Y12_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~12 ; LABCELL_X27_Y11_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|block_read ; FF_X19_Y12_N38 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~14 ; LABCELL_X33_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|comb~0 ; LABCELL_X18_Y11_N57 ; 2 ; Write enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~15 ; LABCELL_X28_Y7_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter~0 ; LABCELL_X21_Y12_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~16 ; LABCELL_X31_Y8_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[3]~1 ; LABCELL_X21_Y12_N36 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~18 ; LABCELL_X35_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem~12 ; LABCELL_X18_Y11_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~19 ; LABCELL_X35_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem~13 ; LABCELL_X18_Y11_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~2 ; LABCELL_X33_Y10_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|block_read ; FF_X23_Y11_N59 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~20 ; LABCELL_X35_Y8_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|comb~0 ; LABCELL_X23_Y11_N36 ; 3 ; Write enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~21 ; LABCELL_X33_Y8_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter~0 ; LABCELL_X23_Y11_N54 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~22 ; LABCELL_X33_Y10_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|data_out~2 ; MLABCELL_X19_Y11_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~23 ; LABCELL_X33_Y10_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem~13 ; LABCELL_X21_Y11_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~25 ; LABCELL_X28_Y13_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem~14 ; LABCELL_X23_Y11_N21 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~27 ; MLABCELL_X32_Y12_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; FF_X22_Y12_N56 ; 64 ; Async. clear ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~28 ; LABCELL_X33_Y11_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|rx_resetn ; FF_X22_Y12_N35 ; 109 ; Async. clear ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~29 ; LABCELL_X28_Y13_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|WideOr7~0 ; LABCELL_X15_Y14_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~3 ; LABCELL_X31_Y8_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always11~0 ; LABCELL_X22_Y14_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~30 ; MLABCELL_X32_Y12_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always1~0 ; MLABCELL_X14_Y14_N33 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~31 ; MLABCELL_X32_Y12_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always2~0 ; MLABCELL_X14_Y14_N30 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~32 ; MLABCELL_X32_Y12_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; LABCELL_X22_Y14_N30 ; 85 ; Clock ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~33 ; MLABCELL_X32_Y12_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|data[9]~0 ; LABCELL_X18_Y14_N48 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~34 ; LABCELL_X33_Y11_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|last_is_data ; FF_X17_Y14_N41 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~35 ; MLABCELL_X32_Y12_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|last_is_data~1 ; LABCELL_X17_Y14_N54 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~37 ; LABCELL_X33_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_control_p_r ; FF_X14_Y14_N26 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~38 ; LABCELL_X33_Y11_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_data ; MLABCELL_X19_Y14_N12 ; 11 ; Clock ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~39 ; LABCELL_X33_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_data_p ; MLABCELL_X19_Y14_N24 ; 11 ; Clock ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~40 ; MLABCELL_X32_Y12_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_flag[8]~9 ; LABCELL_X17_Y14_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~41 ; LABCELL_X33_Y11_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|timecode[7]~0 ; LABCELL_X18_Y14_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~42 ; LABCELL_X33_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|Selector4~2 ; LABCELL_X30_Y12_N42 ; 24 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~44 ; MLABCELL_X32_Y10_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_counter_receive[0]~8 ; LABCELL_X28_Y10_N3 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~45 ; LABCELL_X27_Y11_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_counter_receive[3]~2 ; LABCELL_X28_Y10_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~46 ; LABCELL_X28_Y13_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_flag[1]~2 ; LABCELL_X27_Y10_N36 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~47 ; LABCELL_X28_Y13_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|global_counter_transfer[2]~3 ; LABCELL_X30_Y12_N54 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~48 ; LABCELL_X27_Y11_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|global_counter_transfer[2]~7 ; LABCELL_X28_Y12_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~49 ; LABCELL_X27_Y11_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|last_timein_control_flag_tx~0 ; LABCELL_X28_Y12_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~5 ; MLABCELL_X32_Y12_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|txdata_flagctrl_tx_last[7]~0 ; LABCELL_X27_Y11_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~50 ; LABCELL_X27_Y11_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; LABCELL_X18_Y11_N27 ; 94 ; Async. clear ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~51 ; LABCELL_X27_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X30_Y32_N17 ; 74 ; Async. clear ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~53 ; LABCELL_X27_Y7_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~54 ; MLABCELL_X32_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~55 ; MLABCELL_X32_Y10_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~56 ; LABCELL_X27_Y7_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~57 ; MLABCELL_X32_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~58 ; MLABCELL_X32_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~59 ; MLABCELL_X32_Y10_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~6 ; LABCELL_X33_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~60 ; MLABCELL_X32_Y10_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~62 ; LABCELL_X33_Y10_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~63 ; LABCELL_X27_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~64 ; LABCELL_X28_Y7_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~66 ; LABCELL_X33_Y8_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~67 ; LABCELL_X31_Y8_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~68 ; LABCELL_X33_Y8_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~69 ; LABCELL_X31_Y8_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~70 ; LABCELL_X33_Y8_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~71 ; MLABCELL_X32_Y10_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~72 ; LABCELL_X27_Y11_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~74 ; LABCELL_X35_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~76 ; LABCELL_X35_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~77 ; LABCELL_X33_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~78 ; LABCELL_X33_Y8_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~79 ; LABCELL_X35_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~8 ; MLABCELL_X32_Y10_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~80 ; LABCELL_X33_Y8_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always0~0 ; LABCELL_X31_Y13_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always1~0 ; LABCELL_X27_Y16_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always1~2 ; LABCELL_X31_Y13_N15 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|block_write ; FF_X28_Y11_N26 ; 67 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[5]~0 ; LABCELL_X27_Y16_N51 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[5]~1 ; LABCELL_X31_Y13_N54 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~11 ; LABCELL_X15_Y12_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~13 ; LABCELL_X18_Y10_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~14 ; LABCELL_X15_Y12_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~16 ; MLABCELL_X19_Y10_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~17 ; MLABCELL_X19_Y10_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~19 ; LABCELL_X22_Y10_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~2 ; LABCELL_X15_Y12_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~20 ; LABCELL_X22_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~22 ; LABCELL_X21_Y14_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~23 ; LABCELL_X21_Y14_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~25 ; LABCELL_X22_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~26 ; MLABCELL_X19_Y13_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~28 ; LABCELL_X15_Y12_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~29 ; LABCELL_X17_Y12_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~30 ; LABCELL_X17_Y10_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~31 ; LABCELL_X17_Y12_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~32 ; LABCELL_X17_Y10_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~33 ; LABCELL_X17_Y12_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~34 ; LABCELL_X17_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~36 ; MLABCELL_X19_Y10_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~38 ; LABCELL_X17_Y10_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~39 ; LABCELL_X18_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~4 ; LABCELL_X15_Y12_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~41 ; LABCELL_X22_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~43 ; LABCELL_X22_Y11_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~44 ; LABCELL_X17_Y10_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~45 ; LABCELL_X17_Y12_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~46 ; LABCELL_X17_Y10_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~47 ; LABCELL_X22_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~49 ; LABCELL_X15_Y12_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~51 ; LABCELL_X15_Y12_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~52 ; LABCELL_X15_Y12_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~53 ; LABCELL_X15_Y12_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~54 ; MLABCELL_X19_Y10_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~55 ; LABCELL_X15_Y12_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~56 ; LABCELL_X18_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~57 ; LABCELL_X15_Y12_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~58 ; MLABCELL_X19_Y13_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~59 ; MLABCELL_X19_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~6 ; LABCELL_X15_Y12_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~60 ; LABCELL_X22_Y10_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~61 ; LABCELL_X22_Y10_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~62 ; MLABCELL_X19_Y13_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~63 ; MLABCELL_X19_Y13_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~64 ; MLABCELL_X19_Y13_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~65 ; LABCELL_X22_Y11_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~66 ; LABCELL_X15_Y12_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~67 ; LABCELL_X17_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~68 ; LABCELL_X17_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~69 ; LABCELL_X17_Y12_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~7 ; LABCELL_X15_Y12_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~70 ; LABCELL_X15_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~71 ; LABCELL_X15_Y12_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~72 ; LABCELL_X17_Y10_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~73 ; LABCELL_X17_Y11_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~74 ; LABCELL_X17_Y10_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~75 ; LABCELL_X18_Y10_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~76 ; MLABCELL_X19_Y10_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~77 ; LABCELL_X22_Y11_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~78 ; LABCELL_X17_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~79 ; LABCELL_X17_Y12_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~80 ; MLABCELL_X19_Y10_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~81 ; LABCELL_X22_Y11_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~9 ; MLABCELL_X19_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|always1~0 ; LABCELL_X21_Y14_N36 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|block_write ; FF_X21_Y14_N53 ; 45 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[5]~0 ; LABCELL_X21_Y14_N27 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; FF_X28_Y16_N44 ; 65 ; Async. clear ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|rx_resetn ; FF_X28_Y14_N17 ; 109 ; Async. clear ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|WideOr7~0 ; LABCELL_X35_Y15_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always11~0 ; MLABCELL_X32_Y15_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always1~0 ; LABCELL_X31_Y15_N33 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always2~0 ; LABCELL_X31_Y15_N24 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; LABCELL_X31_Y15_N39 ; 85 ; Clock ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|data[9]~0 ; MLABCELL_X32_Y15_N48 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|last_is_data ; FF_X32_Y15_N56 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|last_is_data~1 ; MLABCELL_X32_Y15_N57 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_control_p_r ; FF_X31_Y15_N14 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_data ; LABCELL_X30_Y15_N12 ; 11 ; Clock ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_data_p ; LABCELL_X30_Y15_N27 ; 11 ; Clock ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_flag[8]~2 ; LABCELL_X31_Y15_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|timecode[7]~0 ; LABCELL_X31_Y15_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|Selector4~2 ; LABCELL_X17_Y15_N45 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_counter_receive[0]~6 ; MLABCELL_X14_Y14_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_counter_receive[5]~1 ; MLABCELL_X14_Y14_N27 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_flag[1]~2 ; MLABCELL_X14_Y16_N36 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|global_counter_transfer[0]~4 ; LABCELL_X17_Y16_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|global_counter_transfer[0]~8 ; LABCELL_X17_Y16_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|last_timein_control_flag_tx~1 ; LABCELL_X17_Y16_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|txdata_flagctrl_tx_last[7]~0 ; LABCELL_X17_Y15_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; LABCELL_X28_Y16_N15 ; 1232 ; Async. clear ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X21_Y27_N47 ; 74 ; Async. clear ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X27_Y1_N38 ; 3025 ; Async. clear ; yes ; Global Clock ; GCLK6 ; -- ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X27_Y1_N38 ; 3025 ; Async. clear ; yes ; Global Clock ; GCLK6 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:auto_start|always0~0 ; MLABCELL_X19_Y28_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:auto_start|always0~0 ; LABCELL_X18_Y30_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx|always0~0 ; LABCELL_X18_Y28_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx|always0~0 ; MLABCELL_X25_Y30_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:link_disable|always0~0 ; LABCELL_X21_Y27_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:link_disable|always0~0 ; LABCELL_X23_Y26_N51 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:link_start|always0~0 ; MLABCELL_X19_Y32_N30 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:link_start|always0~0 ; LABCELL_X28_Y33_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable|always0~0 ; LABCELL_X30_Y21_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable|always0~0 ; MLABCELL_X14_Y24_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx|always0~0 ; MLABCELL_X25_Y24_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx|always0~0 ; LABCELL_X21_Y23_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel|always0~0 ; MLABCELL_X25_Y19_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel|always0~0 ; LABCELL_X13_Y20_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK10 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK10 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|always0~0 ; LABCELL_X18_Y26_N36 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|always0~0 ; LABCELL_X11_Y28_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X13_Y26_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y30_N42 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|always0~0 ; LABCELL_X13_Y26_N12 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X19_Y32_N24 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y18_N45 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y19_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y18_N39 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|always0~0 ; LABCELL_X13_Y19_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y16_N9 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X25_Y17_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|always0~0 ; LABCELL_X17_Y19_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y25_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y17_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y19_N21 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|always0~0 ; LABCELL_X17_Y17_N42 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X25_Y21_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X13_Y30_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y20_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X13_Y30_N9 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X13_Y33_N18 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X18_Y18_N12 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y16_N21 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y18_N51 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X25_Y38_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y30_N27 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y32_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X17_Y30_N9 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y32_N21 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y37_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y36_N33 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X17_Y37_N48 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X15_Y37_N9 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y34_N21 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X21_Y34_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X17_Y34_N27 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X21_Y34_N21 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y35_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y34_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y35_N57 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y34_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X13_Y36_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X10_Y33_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X13_Y35_N9 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X7_Y33_N3 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y18_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X27_Y17_N9 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|always0~0 ; LABCELL_X10_Y20_N3 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y17_N48 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y26_N15 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y18_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|always0~0 ; LABCELL_X15_Y26_N57 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|always0~0 ; LABCELL_X11_Y28_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|always0~0 ; LABCELL_X18_Y26_N39 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y25_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y25_N39 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X19_Y25_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X21_Y33_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X27_Y34_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y32_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|always0~0 ; LABCELL_X27_Y34_N6 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X18_Y33_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y31_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X19_Y36_N24 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y35_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X13_Y18_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y18_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X9_Y31_N54 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X7_Y32_N21 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y16_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|always0~0 ; LABCELL_X21_Y19_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|always0~0 ; LABCELL_X21_Y17_N12 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|always0~0 ; LABCELL_X17_Y19_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|always0~0 ; LABCELL_X21_Y21_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y24_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|always0~0 ; LABCELL_X21_Y21_N6 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y22_N9 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|always0~0 ; LABCELL_X21_Y33_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y38_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|always0~0 ; LABCELL_X22_Y33_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|always0~0 ; LABCELL_X22_Y38_N18 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y22_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y20_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y22_N45 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X22_Y20_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X21_Y24_N27 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y24_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X21_Y24_N9 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X19_Y24_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X25_Y28_N9 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y29_N15 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X25_Y28_N12 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y31_N18 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y23_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y24_N3 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y19_N27 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X14_Y20_N57 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X18_Y21_N9 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y24_N54 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y21_N3 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y24_N45 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X18_Y20_N30 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y21_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y17_N39 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y21_N0 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X10_Y30_N36 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X13_Y33_N27 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X10_Y30_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X13_Y33_N21 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y20_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y36_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y20_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y36_N9 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X25_Y32_N33 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y30_N39 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X22_Y30_N9 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X28_Y32_N33 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y37_N48 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X17_Y37_N6 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y37_N9 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y37_N15 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y34_N9 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y34_N0 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y34_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y34_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X25_Y35_N48 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X10_Y34_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X25_Y35_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X10_Y34_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X11_Y36_N3 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X8_Y34_N48 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X10_Y36_N24 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X7_Y34_N48 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X10_Y21_N33 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X28_Y23_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X10_Y21_N36 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X28_Y20_N21 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X25_Y26_N12 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y27_N6 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y26_N51 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X15_Y27_N45 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X25_Y29_N24 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y28_N39 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y27_N6 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y26_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X25_Y32_N24 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y32_N51 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y32_N36 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y32_N21 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y31_N30 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X18_Y35_N54 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X22_Y36_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X15_Y35_N48 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X11_Y31_N42 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X9_Y35_N18 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X11_Y31_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X9_Y35_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X28_Y19_N24 ; 37 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X25_Y24_N18 ; 37 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y19_N3 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y19_N36 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X25_Y21_N54 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y24_N0 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X25_Y21_N27 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y22_N15 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y33_N36 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y38_N15 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y33_N48 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y38_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y25_N27 ; 38 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y23_N45 ; 38 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y25_N24 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X25_Y22_N9 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X28_Y26_N51 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y27_N0 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X28_Y24_N9 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y23_N48 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X13_Y26_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y30_N57 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y18_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X13_Y19_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y19_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y25_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y17_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y21_N15 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X13_Y30_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X14_Y33_N36 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y18_N21 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X25_Y38_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y30_N51 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y32_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X14_Y37_N57 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y37_N57 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y34_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X21_Y33_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y35_N3 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X14_Y34_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X13_Y35_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X7_Y33_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X11_Y20_N57 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y17_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y26_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X10_Y28_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y25_N0 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y25_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y32_N30 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y34_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y37_N51 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X10_Y35_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X9_Y31_N51 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X6_Y32_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X21_Y17_N36 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y19_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X21_Y21_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X14_Y22_N30 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X22_Y33_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X22_Y38_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y22_N15 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X22_Y20_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X21_Y24_N57 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y24_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|internal_valid~0 ; LABCELL_X23_Y31_N18 ; 29 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|internal_valid~0 ; MLABCELL_X19_Y31_N45 ; 29 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0 ; MLABCELL_X25_Y31_N54 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0 ; LABCELL_X22_Y31_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|internal_valid~0 ; LABCELL_X28_Y27_N36 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|internal_valid~0 ; LABCELL_X30_Y27_N36 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 ; LABCELL_X28_Y28_N9 ; 27 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 ; LABCELL_X28_Y27_N3 ; 27 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0 ; LABCELL_X28_Y28_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0 ; LABCELL_X28_Y27_N54 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|update_grant~0 ; LABCELL_X27_Y31_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|update_grant~0 ; MLABCELL_X19_Y31_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|update_grant~0 ; LABCELL_X22_Y31_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|update_grant~0 ; MLABCELL_X19_Y35_N21 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|update_grant~0 ; LABCELL_X21_Y31_N42 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|update_grant~0 ; LABCELL_X10_Y31_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|top_priority_reg~1 ; MLABCELL_X25_Y32_N42 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X28_Y30_N12 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|update_grant~0 ; MLABCELL_X25_Y32_N48 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|update_grant~0 ; LABCELL_X27_Y30_N33 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|update_grant~0 ; MLABCELL_X25_Y35_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|update_grant~0 ; LABCELL_X10_Y34_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|update_grant~0 ; LABCELL_X21_Y34_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|update_grant~0 ; MLABCELL_X19_Y35_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X28_Y33_N45 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X27_Y32_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|update_grant~0 ; MLABCELL_X25_Y32_N39 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|update_grant~0 ; LABCELL_X27_Y32_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X27_Y28_N54 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y29_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|update_grant~0 ; LABCELL_X27_Y28_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|update_grant~0 ; LABCELL_X23_Y29_N42 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|top_priority_reg~1 ; MLABCELL_X25_Y29_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y28_N42 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|update_grant~0 ; MLABCELL_X25_Y29_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|update_grant~0 ; LABCELL_X23_Y28_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X27_Y25_N42 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y23_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|update_grant~0 ; LABCELL_X27_Y25_N12 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|update_grant~0 ; LABCELL_X23_Y23_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X28_Y26_N12 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X22_Y27_N57 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|update_grant~0 ; LABCELL_X28_Y26_N42 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|update_grant~0 ; LABCELL_X22_Y27_N33 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|update_grant~0 ; LABCELL_X27_Y34_N51 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|update_grant~0 ; LABCELL_X10_Y34_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|update_grant~0 ; LABCELL_X27_Y34_N42 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|update_grant~0 ; MLABCELL_X19_Y33_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X28_Y19_N3 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|top_priority_reg~1 ; MLABCELL_X25_Y24_N48 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|update_grant~0 ; LABCELL_X28_Y19_N57 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|update_grant~0 ; MLABCELL_X25_Y24_N15 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|top_priority_reg~0 ; MLABCELL_X25_Y21_N36 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X22_Y24_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|update_grant~0 ; MLABCELL_X25_Y21_N45 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|update_grant~0 ; LABCELL_X22_Y24_N48 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|update_grant~0 ; LABCELL_X23_Y33_N9 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|update_grant~0 ; MLABCELL_X19_Y38_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|update_grant~0 ; MLABCELL_X19_Y20_N9 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|update_grant~0 ; LABCELL_X23_Y36_N27 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X27_Y23_N3 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y24_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|update_grant~0 ; LABCELL_X27_Y23_N36 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|update_grant~0 ; LABCELL_X23_Y24_N42 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|update_grant~0 ; LABCELL_X21_Y31_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|update_grant~0 ; LABCELL_X27_Y25_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|update_grant~0 ; LABCELL_X18_Y19_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|update_grant~0 ; LABCELL_X23_Y21_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|update_grant~0 ; LABCELL_X17_Y21_N33 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|update_grant~0 ; LABCELL_X27_Y24_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg~0 ; MLABCELL_X25_Y26_N54 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X21_Y27_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|update_grant~0 ; MLABCELL_X25_Y26_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|update_grant~0 ; LABCELL_X21_Y27_N57 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y2_N1 ; 24 ; Clock ; yes ; Global Clock ; GCLK11 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Clock ; yes ; Global Clock ; GCLK11 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data|always0~0 ; LABCELL_X27_Y18_N3 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data|always0~0 ; LABCELL_X18_Y20_N3 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx|always0~0 ; LABCELL_X23_Y22_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx|always0~0 ; LABCELL_X22_Y22_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Global & Other Fast Signals ;
|
; Global & Other Fast Signals ;
|
| Line 1836... |
Line 1954... |
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
; FPGA_CLK1_50 ; PIN_Y13 ; 3124 ; Global Clock ; GCLK5 ; -- ;
|
; FPGA_CLK1_50 ; PIN_Y13 ; 3124 ; Global Clock ; GCLK5 ; -- ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X27_Y1_N38 ; 3025 ; Global Clock ; GCLK6 ; -- ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X27_Y1_N38 ; 3025 ; Global Clock ; GCLK6 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Global Clock ; GCLK10 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Global Clock ; GCLK10 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y2_N1 ; 24 ; Global Clock ; GCLK11 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Global Clock ; GCLK11 ; -- ;
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------+
|
; Fitter RAM Summary ;
|
; Non-Global High Fan-Out Signals ;
|
+---------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+-----------------+----------------------+-----------------+-----------------+----------+------------------------+---------------------------------------------+
|
+---------------------------------------------------------------+---------+
|
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ;
|
; Name ; Fan-Out ;
|
+---------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+-----------------+----------------------+-----------------+-----------------+----------+------------------------+---------------------------------------------+
|
+---------------------------------------------------------------+---------+
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|altsyncram:mem_rtl_0|altsyncram_pfo1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 64 ; 9 ; 64 ; 9 ; yes ; no ; yes ; no ; 576 ; 64 ; 9 ; 64 ; 9 ; 576 ; 1 ; 0 ; None ; M10K_X20_Y12_N0 ; Old data ; New data ; New data ; Off ; No ; No - Unsupported Mixed Feed Through Setting ;
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1270 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|altsyncram:mem_rtl_0|altsyncram_pfo1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 64 ; 9 ; 64 ; 9 ; yes ; no ; yes ; no ; 576 ; 64 ; 9 ; 64 ; 9 ; 576 ; 1 ; 0 ; None ; M10K_X20_Y11_N0 ; Old data ; New data ; New data ; Off ; No ; No - Unsupported Mixed Feed Through Setting ;
|
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; 1232 ;
|
+---------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+-----------------+----------------------+-----------------+-----------------+----------+------------------------+---------------------------------------------+
|
+---------------------------------------------------------------+---------+
|
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
|
|
|
|
|
|
+-----------------------------------------------------------------------+
|
+-----------------------------------------------------------------------+
|
; Routing Usage Summary ;
|
; Routing Usage Summary ;
|
+---------------------------------------------+-------------------------+
|
+---------------------------------------------+-------------------------+
|
; Routing Resource Type ; Usage ;
|
; Routing Resource Type ; Usage ;
|
+---------------------------------------------+-------------------------+
|
+---------------------------------------------+-------------------------+
|
; Block interconnects ; 7,434 / 130,276 ( 6 % ) ;
|
; Block interconnects ; 9,946 / 130,276 ( 8 % ) ;
|
; C12 interconnects ; 110 / 6,848 ( 2 % ) ;
|
; C12 interconnects ; 143 / 6,848 ( 2 % ) ;
|
; C2 interconnects ; 1,713 / 51,436 ( 3 % ) ;
|
; C2 interconnects ; 2,297 / 51,436 ( 4 % ) ;
|
; C4 interconnects ; 1,039 / 25,120 ( 4 % ) ;
|
; C4 interconnects ; 1,292 / 25,120 ( 5 % ) ;
|
; DQS bus muxes ; 0 / 19 ( 0 % ) ;
|
; DQS bus muxes ; 0 / 19 ( 0 % ) ;
|
; DQS-18 I/O buses ; 0 / 19 ( 0 % ) ;
|
; DQS-18 I/O buses ; 0 / 19 ( 0 % ) ;
|
; DQS-9 I/O buses ; 0 / 19 ( 0 % ) ;
|
; DQS-9 I/O buses ; 0 / 19 ( 0 % ) ;
|
; Direct links ; 1,365 / 130,276 ( 1 % ) ;
|
; Direct links ; 1,482 / 130,276 ( 1 % ) ;
|
; Global clocks ; 4 / 16 ( 25 % ) ;
|
; Global clocks ; 4 / 16 ( 25 % ) ;
|
; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
|
; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
|
; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
|
; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
|
; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
|
; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
|
; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
|
; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
|
| Line 1919... |
Line 2036... |
; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
|
; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
|
; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
|
; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
|
; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
|
; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
|
; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
|
; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
|
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
; Local interconnects ; 3,191 / 31,760 ( 10 % ) ;
|
; Local interconnects ; 3,498 / 31,760 ( 11 % ) ;
|
; Quadrant clocks ; 0 / 72 ( 0 % ) ;
|
; Quadrant clocks ; 0 / 72 ( 0 % ) ;
|
; R14 interconnects ; 140 / 6,046 ( 2 % ) ;
|
; R14 interconnects ; 179 / 6,046 ( 3 % ) ;
|
; R14/C12 interconnect drivers ; 201 / 8,584 ( 2 % ) ;
|
; R14/C12 interconnect drivers ; 267 / 8,584 ( 3 % ) ;
|
; R3 interconnects ; 2,564 / 56,712 ( 5 % ) ;
|
; R3 interconnects ; 3,386 / 56,712 ( 6 % ) ;
|
; R6 interconnects ; 4,186 / 131,000 ( 3 % ) ;
|
; R6 interconnects ; 5,364 / 131,000 ( 4 % ) ;
|
; Spine clocks ; 8 / 150 ( 5 % ) ;
|
; Spine clocks ; 9 / 150 ( 6 % ) ;
|
; Wire stub REs ; 0 / 6,650 ( 0 % ) ;
|
; Wire stub REs ; 0 / 6,650 ( 0 % ) ;
|
+---------------------------------------------+-------------------------+
|
+---------------------------------------------+-------------------------+
|
|
|
|
|
+------------------------------------------+
|
+------------------------------------------+
|
| Line 1989... |
Line 2106... |
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
; Total Pass ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 19 ; 16 ;
|
; Total Pass ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 19 ; 16 ;
|
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
; Total Inapplicable ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 0 ; 3 ;
|
; Total Inapplicable ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 0 ; 3 ;
|
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
; LED[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
|
; LED[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
|
; dout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; dout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; sout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; sout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
|
; LED[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
|
; LED[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| Line 2059... |
Line 2176... |
+------------------------------------------------------------+
|
+------------------------------------------------------------+
|
; Estimated Delay Added for Hold Timing Summary ;
|
; Estimated Delay Added for Hold Timing Summary ;
|
+-----------------+----------------------+-------------------+
|
+-----------------+----------------------+-------------------+
|
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
|
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
|
+-----------------+----------------------+-------------------+
|
+-----------------+----------------------+-------------------+
|
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 431.9 ;
|
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 417.7 ;
|
+-----------------+----------------------+-------------------+
|
+-----------------+----------------------+-------------------+
|
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
|
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
|
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
|
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Estimated Delay Added for Hold Timing Details ;
|
; Estimated Delay Added for Hold Timing Details ;
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
; Source Register ; Destination Register ; Delay Added in ns ;
|
; Source Register ; Destination Register ; Delay Added in ns ;
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.486 ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2495 ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[3] ; 0.427 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.464 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.370 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.442 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.362 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.429 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|packet_in_progress ; 0.351 ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2495 ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[15] ; 0.389 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|packet_in_progress ; 0.345 ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2494 ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[5] ; 0.389 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; 0.341 ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2399 ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] ; 0.335 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; 0.338 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.332 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[4] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[4] ; 0.331 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.328 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; 0.325 ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2469 ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[8] ; 0.325 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.323 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2401 ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] ; 0.322 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; 0.321 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2468 ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[9] ; 0.314 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.315 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.311 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.312 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.309 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.312 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.309 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.312 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.309 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.311 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.308 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.311 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.307 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.311 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.307 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.309 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.307 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.308 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.307 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.294 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] ; 0.294 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.294 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.293 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.299 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.293 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|wait_latency_counter[1] ; 0.295 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.293 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.294 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.294 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.294 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.294 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.293 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.293 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.293 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|saved_grant[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.291 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.291 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.291 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][75] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][77] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.290 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.290 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.290 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.290 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.290 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][74] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[4] ; 0.290 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.290 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.290 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.290 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0] ; 0.290 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.290 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.290 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.290 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] ; 0.290 ;
|
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2398 ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.290 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] ; 0.289 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][110] ; 0.289 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.289 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.289 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.289 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.289 ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.289 ;
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
|
Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
|
|
|
|
|
+-----------------+
|
+-----------------+
|
| Line 2185... |
Line 2302... |
Info (21077): Low junction temperature is 0 degrees C
|
Info (21077): Low junction temperature is 0 degrees C
|
Info (21077): High junction temperature is 85 degrees C
|
Info (21077): High junction temperature is 85 degrees C
|
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
|
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
|
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
|
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
|
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
|
|
Info (184025): 4 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins.
|
Info (184025): 4 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins.
|
Info (184026): differential I/O pin "dout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "dout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 9
|
Info (184026): differential I/O pin "dout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "dout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 9
|
Info (184026): differential I/O pin "sout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 10
|
Info (184026): differential I/O pin "sout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 10
|
Info (184026): differential I/O pin "din_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "din_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 5
|
Info (184026): differential I/O pin "din_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "din_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 5
|
Info (184026): differential I/O pin "sin_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sin_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 6
|
Info (184026): differential I/O pin "sin_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sin_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 6
|
| Line 2227... |
Line 2343... |
Info (176222): Fitter will not automatically pack the registers into I/Os.
|
Info (176222): Fitter will not automatically pack the registers into I/Os.
|
Info (176235): Finished register packing
|
Info (176235): Finished register packing
|
Extra Info (176219): No registers were packed into other blocks
|
Extra Info (176219): No registers were packed into other blocks
|
Info (223000): Starting Vectorless Power Activity Estimation
|
Info (223000): Starting Vectorless Power Activity Estimation
|
Info (223001): Completed Vectorless Power Activity Estimation
|
Info (223001): Completed Vectorless Power Activity Estimation
|
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:15
|
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:16
|
Warning (170136): Design uses Placement Effort Multiplier = 40.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt.
|
Warning (170136): Design uses Placement Effort Multiplier = 90.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt.
|
Info (170189): Fitter placement preparation operations beginning
|
Info (170189): Fitter placement preparation operations beginning
|
Info (223000): Starting Vectorless Power Activity Estimation
|
Info (223000): Starting Vectorless Power Activity Estimation
|
Info (223001): Completed Vectorless Power Activity Estimation
|
Info (223001): Completed Vectorless Power Activity Estimation
|
Info (14951): The Fitter is using Advanced Physical Optimization.
|
Info (14951): The Fitter is using Advanced Physical Optimization.
|
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:24
|
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:28
|
|
Info (223000): Starting Vectorless Power Activity Estimation
|
|
Info (223001): Completed Vectorless Power Activity Estimation
|
Info (170191): Fitter placement operations beginning
|
Info (170191): Fitter placement operations beginning
|
Info (170137): Fitter placement was successful
|
Info (170137): Fitter placement was successful
|
Info (170192): Fitter placement operations ending: elapsed time is 00:00:59
|
Info (170192): Fitter placement operations ending: elapsed time is 00:01:55
|
Info (170193): Fitter routing operations beginning
|
Info (170193): Fitter routing operations beginning
|
Info (223000): Starting Vectorless Power Activity Estimation
|
Info (223000): Starting Vectorless Power Activity Estimation
|
Info (223001): Completed Vectorless Power Activity Estimation
|
Info (223001): Completed Vectorless Power Activity Estimation
|
Info (170195): Router estimated average interconnect usage is 2% of the available device resources
|
Info (170195): Router estimated average interconnect usage is 3% of the available device resources
|
Info (170196): Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X11_Y24 to location X22_Y36
|
Info (170196): Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y24 to location X22_Y36
|
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
Info (170200): Optimizations that may affect the design's timing were skipped
|
Info (170200): Optimizations that may affect the design's timing were skipped
|
Info (170194): Fitter routing operations ending: elapsed time is 00:00:32
|
Info (170194): Fitter routing operations ending: elapsed time is 00:00:40
|
Info (11888): Total time spent on timing analysis during the Fitter is 13.56 seconds.
|
Info (11888): Total time spent on timing analysis during the Fitter is 16.50 seconds.
|
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
|
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05
|
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
Info (144001): Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg
|
Info (144001): Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg
|
Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings
|
Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings
|
Info: Peak virtual memory: 2094 megabytes
|
Info: Peak virtual memory: 2064 megabytes
|
Info: Processing ended: Thu Aug 24 22:41:05 2017
|
Info: Processing ended: Fri Sep 15 08:17:51 2017
|
Info: Elapsed time: 00:03:17
|
Info: Elapsed time: 00:04:44
|
Info: Total CPU time (on all processors): 00:05:45
|
Info: Total CPU time (on all processors): 00:08:19
|
|
|
|
|
+----------------------------+
|
+----------------------------+
|
; Fitter Suppressed Messages ;
|
; Fitter Suppressed Messages ;
|
+----------------------------+
|
+----------------------------+
|
