| Line 1... |
Line 1... |
Flow report for spw_fifo_ulight
|
Flow report for spw_fifo_ulight
|
Thu Aug 24 22:42:14 2017
|
Fri Sep 15 08:19:20 2017
|
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition
|
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition
|
|
|
|
|
---------------------
|
---------------------
|
; Table of Contents ;
|
; Table of Contents ;
|
| Line 39... |
Line 39... |
|
|
|
|
+-------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------+
|
; Flow Summary ;
|
; Flow Summary ;
|
+---------------------------------+---------------------------------------------+
|
+---------------------------------+---------------------------------------------+
|
; Flow Status ; Successful - Thu Aug 24 22:42:14 2017 ;
|
; Flow Status ; Successful - Fri Sep 15 08:19:20 2017 ;
|
; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;
|
; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;
|
; Revision Name ; spw_fifo_ulight ;
|
; Revision Name ; spw_fifo_ulight ;
|
; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
|
; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
|
; Family ; Cyclone V ;
|
; Family ; Cyclone V ;
|
; Device ; 5CSEMA4U23C6 ;
|
; Device ; 5CSEMA4U23C6 ;
|
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
; Logic utilization (in ALMs) ; 2,724 / 15,880 ( 17 % ) ;
|
; Logic utilization (in ALMs) ; 3,209 / 15,880 ( 20 % ) ;
|
; Total registers ; 3603 ;
|
; Total registers ; 4692 ;
|
; Total pins ; 19 / 314 ( 6 % ) ;
|
; Total pins ; 19 / 314 ( 6 % ) ;
|
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
; Total block memory bits ; 1,152 / 2,764,800 ( < 1 % ) ;
|
; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;
|
; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
|
; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
|
; Total HSSI RX PCSs ; 0 ;
|
; Total HSSI RX PCSs ; 0 ;
|
; Total HSSI PMA RX Deserializers ; 0 ;
|
; Total HSSI PMA RX Deserializers ; 0 ;
|
; Total HSSI TX PCSs ; 0 ;
|
; Total HSSI TX PCSs ; 0 ;
|
; Total HSSI PMA TX Serializers ; 0 ;
|
; Total HSSI PMA TX Serializers ; 0 ;
|
| Line 66... |
Line 66... |
+-----------------------------------------+
|
+-----------------------------------------+
|
; Flow Settings ;
|
; Flow Settings ;
|
+-------------------+---------------------+
|
+-------------------+---------------------+
|
; Option ; Setting ;
|
; Option ; Setting ;
|
+-------------------+---------------------+
|
+-------------------+---------------------+
|
; Start date & time ; 08/24/2017 22:32:50 ;
|
; Start date & time ; 09/15/2017 08:07:49 ;
|
; Main task ; Compilation ;
|
; Main task ; Compilation ;
|
; Revision Name ; spw_fifo_ulight ;
|
; Revision Name ; spw_fifo_ulight ;
|
+-------------------+---------------------+
|
+-------------------+---------------------+
|
|
|
|
|
| Line 83... |
Line 83... |
; ALLOW_REGISTER_MERGING ; Off ; On ; -- ; -- ;
|
; ALLOW_REGISTER_MERGING ; Off ; On ; -- ; -- ;
|
; ALLOW_REGISTER_RETIMING ; Off ; On ; -- ; -- ;
|
; ALLOW_REGISTER_RETIMING ; Off ; On ; -- ; -- ;
|
; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ;
|
; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ;
|
; ALLOW_SYNCH_CTRL_USAGE ; Off ; On ; -- ; -- ;
|
; ALLOW_SYNCH_CTRL_USAGE ; Off ; On ; -- ; -- ;
|
; AUTO_DELAY_CHAINS ; Off ; On ; -- ; -- ;
|
; AUTO_DELAY_CHAINS ; Off ; On ; -- ; -- ;
|
; COMPILER_SIGNATURE_ID ; 31032335263289.150362476611918 ; -- ; -- ; -- ;
|
; COMPILER_SIGNATURE_ID ; 31032335263289.150547366508423 ; -- ; -- ; -- ;
|
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
|
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
|
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ;
|
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ;
|
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
|
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
|
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
|
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
|
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
|
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
|
| Line 127... |
Line 127... |
; OPTIMIZE_POWER_DURING_FITTING ; Extra effort ; Normal compilation ; -- ; -- ;
|
; OPTIMIZE_POWER_DURING_FITTING ; Extra effort ; Normal compilation ; -- ; -- ;
|
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
|
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
|
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
|
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
|
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
|
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
|
; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ;
|
; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ;
|
; PLACEMENT_EFFORT_MULTIPLIER ; 40.0 ; 1.0 ; -- ; -- ;
|
; PLACEMENT_EFFORT_MULTIPLIER ; 90.0 ; 1.0 ; -- ; -- ;
|
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
|
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
|
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
|
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
|
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
; REMOVE_DUPLICATE_REGISTERS ; Off ; On ; -- ; -- ;
|
; REMOVE_DUPLICATE_REGISTERS ; Off ; On ; -- ; -- ;
|
; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; Off ; Auto ; -- ; -- ;
|
; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; Off ; Auto ; -- ; -- ;
|
; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;
|
; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;
|
; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ;
|
; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ;
|
|
; SEED ; 893763639 ; 1 ; -- ; -- ;
|
; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.regmap ; -- ; -- ; -- ;
|
; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.regmap ; -- ; -- ; -- ;
|
; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.debuginfo ; -- ; -- ; -- ;
|
; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.debuginfo ; -- ; -- ; -- ;
|
; SLD_INFO ; QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1502975928 ; -- ; ulight_fifo ; -- ;
|
; SLD_INFO ; QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1502975928 ; -- ; ulight_fifo ; -- ;
|
; SOPCINFO_FILE ; ulight_fifo/synthesis/../../ulight_fifo.sopcinfo ; -- ; -- ; -- ;
|
; SOPCINFO_FILE ; ulight_fifo/synthesis/../../ulight_fifo.sopcinfo ; -- ; -- ; -- ;
|
; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;
|
; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;
|
| Line 150... |
Line 151... |
+-------------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------------+
|
; Flow Elapsed Time ;
|
; Flow Elapsed Time ;
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
; Analysis & Synthesis ; 00:01:13 ; 1.3 ; 1332 MB ; 00:01:47 ;
|
; Analysis & Synthesis ; 00:01:16 ; 1.3 ; 1339 MB ; 00:01:53 ;
|
; Fitter ; 00:03:16 ; 1.0 ; 2094 MB ; 00:05:44 ;
|
; Fitter ; 00:04:42 ; 1.0 ; 2064 MB ; 00:08:17 ;
|
; Assembler ; 00:00:16 ; 1.0 ; 1026 MB ; 00:00:10 ;
|
; Assembler ; 00:00:18 ; 1.0 ; 1040 MB ; 00:00:12 ;
|
; TimeQuest Timing Analyzer ; 00:00:40 ; 1.5 ; 1351 MB ; 00:00:57 ;
|
; TimeQuest Timing Analyzer ; 00:00:54 ; 1.5 ; 1351 MB ; 00:01:15 ;
|
; EDA Netlist Writer ; 00:00:07 ; 1.0 ; 1296 MB ; 00:00:07 ;
|
; EDA Netlist Writer ; 00:00:08 ; 1.0 ; 1314 MB ; 00:00:08 ;
|
; Total ; 00:05:32 ; -- ; -- ; 00:08:45 ;
|
; Total ; 00:07:18 ; -- ; -- ; 00:11:45 ;
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
|
|
|
|
+-----------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------+
|
; Flow OS Summary ;
|
; Flow OS Summary ;
|
