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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [altera_mem_if_dll_cyclonev.sv] - Diff between revs 32 and 40

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// (C) 2001-2017 Intel Corporation. All rights reserved.
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors.  Please refer to the applicable
// Intel or its authorized distributors.  Please refer to the applicable
// agreement for further details.
// agreement for further details.
 
 
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// This file instantiates the DLL.
// This file instantiates the DLL.
// ********************************************************************************************************************************
// ********************************************************************************************************************************
 
 
`timescale 1 ps / 1 ps
`timescale 1 ps / 1 ps
 
 
(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_dll; -name IP_TOOL_VERSION 17.0; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_dll; -name IP_TOOL_VERSION 17.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
 
 
 
 
module altera_mem_if_dll_cyclonev (
module altera_mem_if_dll_cyclonev (
        clk,
        clk,
 
 

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