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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [hps_sdram.v] - Diff between revs 32 and 40

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// hps_sdram.v
// hps_sdram.v
 
 
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl.  If you edit it your changes
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl.  If you edit it your changes
// will probably be lost.
// will probably be lost.
// 
// 
// Generated using ACDS version 17.0 598
// Generated using ACDS version 17.1 593
 
 
`timescale 1 ps / 1 ps
`timescale 1 ps / 1 ps
module hps_sdram (
module hps_sdram (
                input  wire        pll_ref_clk,    //  pll_ref_clk.clk
                input  wire        pll_ref_clk,    //  pll_ref_clk.clk
                input  wire        global_reset_n, // global_reset.reset_n
                input  wire        global_reset_n, // global_reset.reset_n

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