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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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);
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localparam RESET_REQUEST_DELAY = 4;
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localparam RESET_REQUEST_DELAY = 4;
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localparam CSR_IP_VERSION_NUMBER = 170;
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localparam CSR_IP_VERSION_NUMBER = 171;
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parameter CSR_ADDR_WIDTH = 8;
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parameter CSR_ADDR_WIDTH = 8;
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parameter CSR_DATA_WIDTH = 32;
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parameter CSR_DATA_WIDTH = 32;
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parameter CSR_BE_WIDTH = 4;
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parameter CSR_BE_WIDTH = 4;
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