// (C) 2001-2017 Intel Corporation. All rights reserved.
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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// This file instantiates the PLL.
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// This file instantiates the PLL.
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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`timescale 1 ps / 1 ps
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`timescale 1 ps / 1 ps
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(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_hps_pll; -name IP_TOOL_VERSION 17.0; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
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(* altera_attribute = "-name IP_TOOL_NAME altera_mem_if_hps_pll; -name IP_TOOL_VERSION 17.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
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// pll_mem_clk: full-rate clock, 0 degree phase shift, clock output to memory
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// pll_mem_clk: full-rate clock, 0 degree phase shift, clock output to memory
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// pll_write_clk: full-rate clock, -90 degree phase shift, clocks write data out to memory
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// pll_write_clk: full-rate clock, -90 degree phase shift, clocks write data out to memory
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module hps_sdram_pll (
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module hps_sdram_pll (
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global_reset_n,
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global_reset_n,
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pll_ref_clk,
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pll_ref_clk,
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pll_mem_clk,
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pll_mem_clk,
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pll_write_clk,
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pll_write_clk,
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pll_write_clk_pre_phy_clk,
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pll_write_clk_pre_phy_clk,
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pll_addr_cmd_clk,
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pll_addr_cmd_clk,
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pll_avl_clk,
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pll_avl_clk,
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pll_config_clk,
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pll_config_clk,
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pll_locked,
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pll_locked,
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afi_clk,
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afi_clk,
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pll_mem_phy_clk,
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pll_mem_phy_clk,
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afi_phy_clk,
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afi_phy_clk,
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pll_avl_phy_clk,
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pll_avl_phy_clk,
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afi_half_clk
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afi_half_clk
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);
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);
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// BEGIN PARAMETER SECTION
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// BEGIN PARAMETER SECTION
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// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver.
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// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver.
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parameter DEVICE_FAMILY = "Cyclone V";
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parameter DEVICE_FAMILY = "Cyclone V";
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parameter IS_HHP_HPS = "true";
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parameter IS_HHP_HPS = "true";
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// Clock settings
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// Clock settings
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parameter GENERIC_PLL = "true";
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parameter GENERIC_PLL = "true";
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parameter REF_CLK_FREQ = "125.0 MHz";
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parameter REF_CLK_FREQ = "125.0 MHz";
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parameter REF_CLK_PERIOD_PS = 8000;
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parameter REF_CLK_PERIOD_PS = 8000;
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parameter PLL_MEM_CLK_FREQ_STR = "300.0 MHz";
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parameter PLL_MEM_CLK_FREQ_STR = "300.0 MHz";
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parameter PLL_WRITE_CLK_FREQ_STR = "300.0 MHz";
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parameter PLL_WRITE_CLK_FREQ_STR = "300.0 MHz";
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parameter PLL_DR_CLK_FREQ_STR = "";
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parameter PLL_DR_CLK_FREQ_STR = "";
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parameter PLL_MEM_CLK_FREQ_SIM_STR = "3334 ps";
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parameter PLL_MEM_CLK_FREQ_SIM_STR = "3334 ps";
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parameter PLL_WRITE_CLK_FREQ_SIM_STR = "3334 ps";
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parameter PLL_WRITE_CLK_FREQ_SIM_STR = "3334 ps";
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parameter PLL_DR_CLK_FREQ_SIM_STR = "0 ps";
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parameter PLL_DR_CLK_FREQ_SIM_STR = "0 ps";
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parameter MEM_CLK_PHASE = "0 ps";
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parameter MEM_CLK_PHASE = "0 ps";
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parameter WRITE_CLK_PHASE = "2500 ps";
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parameter WRITE_CLK_PHASE = "2500 ps";
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parameter DR_CLK_PHASE = "";
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parameter DR_CLK_PHASE = "";
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localparam SIM_FILESET = ("false" == "true");
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localparam SIM_FILESET = ("false" == "true");
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localparam MEM_CLK_FREQ = SIM_FILESET ? PLL_MEM_CLK_FREQ_SIM_STR : PLL_MEM_CLK_FREQ_STR;
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localparam MEM_CLK_FREQ = SIM_FILESET ? PLL_MEM_CLK_FREQ_SIM_STR : PLL_MEM_CLK_FREQ_STR;
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localparam WRITE_CLK_FREQ = SIM_FILESET ? PLL_WRITE_CLK_FREQ_SIM_STR : PLL_WRITE_CLK_FREQ_STR;
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localparam WRITE_CLK_FREQ = SIM_FILESET ? PLL_WRITE_CLK_FREQ_SIM_STR : PLL_WRITE_CLK_FREQ_STR;
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localparam DR_CLK_FREQ = SIM_FILESET ? PLL_DR_CLK_FREQ_SIM_STR : PLL_DR_CLK_FREQ_STR;
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localparam DR_CLK_FREQ = SIM_FILESET ? PLL_DR_CLK_FREQ_SIM_STR : PLL_DR_CLK_FREQ_STR;
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// END PARAMETER SECTION
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// END PARAMETER SECTION
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// BEGIN PORT SECTION
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// BEGIN PORT SECTION
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input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
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input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
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input pll_ref_clk; // PLL reference clock
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input pll_ref_clk; // PLL reference clock
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output pll_mem_clk;
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output pll_mem_clk;
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output pll_write_clk;
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output pll_write_clk;
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output pll_write_clk_pre_phy_clk;
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output pll_write_clk_pre_phy_clk;
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output pll_addr_cmd_clk;
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output pll_addr_cmd_clk;
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output pll_avl_clk;
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output pll_avl_clk;
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output pll_config_clk;
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output pll_config_clk;
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output pll_locked;
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output pll_locked;
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output afi_clk;
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output afi_clk;
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output pll_mem_phy_clk;
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output pll_mem_phy_clk;
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output afi_phy_clk;
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output afi_phy_clk;
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output pll_avl_phy_clk;
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output pll_avl_phy_clk;
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output afi_half_clk;
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output afi_half_clk;
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// END PORT SECTION
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// END PORT SECTION
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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generate
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generate
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if (SIM_FILESET) begin
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if (SIM_FILESET) begin
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wire fbout;
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wire fbout;
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generic_pll pll1 (
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generic_pll pll1 (
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.refclk({pll_ref_clk}),
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.refclk({pll_ref_clk}),
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.rst(~global_reset_n),
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.rst(~global_reset_n),
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.fbclk(fbout),
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.fbclk(fbout),
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.outclk(pll_mem_clk),
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.outclk(pll_mem_clk),
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.fboutclk(fbout),
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.fboutclk(fbout),
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.locked(pll_locked)
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.locked(pll_locked)
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);
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);
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defparam pll1.reference_clock_frequency = REF_CLK_FREQ,
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defparam pll1.reference_clock_frequency = REF_CLK_FREQ,
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pll1.output_clock_frequency = MEM_CLK_FREQ,
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pll1.output_clock_frequency = MEM_CLK_FREQ,
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pll1.phase_shift = MEM_CLK_PHASE,
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pll1.phase_shift = MEM_CLK_PHASE,
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pll1.duty_cycle = 50;
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pll1.duty_cycle = 50;
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generic_pll pll2 (
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generic_pll pll2 (
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.refclk({pll_ref_clk}),
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.refclk({pll_ref_clk}),
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.rst(~global_reset_n),
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.rst(~global_reset_n),
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.fbclk(fbout),
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.fbclk(fbout),
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.outclk(pll_write_clk),
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.outclk(pll_write_clk),
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.fboutclk(),
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.fboutclk(),
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.locked()
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.locked()
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);
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);
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defparam pll2.reference_clock_frequency = REF_CLK_FREQ,
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defparam pll2.reference_clock_frequency = REF_CLK_FREQ,
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pll2.output_clock_frequency = WRITE_CLK_FREQ,
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pll2.output_clock_frequency = WRITE_CLK_FREQ,
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pll2.phase_shift = WRITE_CLK_PHASE,
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pll2.phase_shift = WRITE_CLK_PHASE,
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pll2.duty_cycle = 50;
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pll2.duty_cycle = 50;
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end else begin
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end else begin
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wire [4-1:0] clk_out;
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wire [4-1:0] clk_out;
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if (DEVICE_FAMILY == "Arria V") begin
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if (DEVICE_FAMILY == "Arria V") begin
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arriav_hps_sdram_pll pll (
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arriav_hps_sdram_pll pll (
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.clk_out(clk_out)
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.clk_out(clk_out)
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);
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);
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defparam pll.reference_clock_frequency = REF_CLK_FREQ,
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defparam pll.reference_clock_frequency = REF_CLK_FREQ,
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pll.clk0_frequency = MEM_CLK_FREQ,
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pll.clk0_frequency = MEM_CLK_FREQ,
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pll.clk0_phase_shift = MEM_CLK_PHASE,
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pll.clk0_phase_shift = MEM_CLK_PHASE,
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pll.clk1_frequency = WRITE_CLK_FREQ,
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pll.clk1_frequency = WRITE_CLK_FREQ,
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pll.clk1_phase_shift = WRITE_CLK_PHASE,
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pll.clk1_phase_shift = WRITE_CLK_PHASE,
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pll.clk2_frequency = DR_CLK_FREQ,
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pll.clk2_frequency = DR_CLK_FREQ,
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pll.clk2_phase_shift = DR_CLK_PHASE;
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pll.clk2_phase_shift = DR_CLK_PHASE;
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end else if (DEVICE_FAMILY == "Cyclone V") begin
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end else if (DEVICE_FAMILY == "Cyclone V") begin
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cyclonev_hps_sdram_pll pll (
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cyclonev_hps_sdram_pll pll (
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.clk_out(clk_out)
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.clk_out(clk_out)
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);
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);
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defparam pll.reference_clock_frequency = REF_CLK_FREQ,
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defparam pll.reference_clock_frequency = REF_CLK_FREQ,
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pll.clk0_frequency = MEM_CLK_FREQ,
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pll.clk0_frequency = MEM_CLK_FREQ,
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pll.clk0_phase_shift = MEM_CLK_PHASE,
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pll.clk0_phase_shift = MEM_CLK_PHASE,
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pll.clk1_frequency = WRITE_CLK_FREQ,
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pll.clk1_frequency = WRITE_CLK_FREQ,
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pll.clk1_phase_shift = WRITE_CLK_PHASE,
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pll.clk1_phase_shift = WRITE_CLK_PHASE,
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pll.clk2_frequency = DR_CLK_FREQ,
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pll.clk2_frequency = DR_CLK_FREQ,
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pll.clk2_phase_shift = DR_CLK_PHASE;
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pll.clk2_phase_shift = DR_CLK_PHASE;
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end else begin
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end else begin
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unknown_family_hps_sdram_pll pll();
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unknown_family_hps_sdram_pll pll();
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end
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end
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assign pll_mem_clk = clk_out[0];
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assign pll_mem_clk = clk_out[0];
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assign pll_write_clk = clk_out[1];
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assign pll_write_clk = clk_out[1];
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assign pll_dr_clk = clk_out[2];
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assign pll_dr_clk = clk_out[2];
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end
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end
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endgenerate
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endgenerate
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assign pll_addr_cmd_clk = pll_mem_clk;
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assign pll_addr_cmd_clk = pll_mem_clk;
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assign pll_avl_clk = pll_mem_clk;
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assign pll_avl_clk = pll_mem_clk;
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assign pll_config_clk = pll_mem_clk;
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assign pll_config_clk = pll_mem_clk;
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assign afi_clk = pll_mem_clk;
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assign afi_clk = pll_mem_clk;
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assign pll_mem_phy_clk = pll_mem_clk;
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assign pll_mem_phy_clk = pll_mem_clk;
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assign afi_phy_clk = pll_mem_clk;
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assign afi_phy_clk = pll_mem_clk;
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assign pll_avl_phy_clk = pll_mem_clk;
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assign pll_avl_phy_clk = pll_mem_clk;
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assign afi_half_clk = pll_mem_clk;
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assign afi_half_clk = pll_mem_clk;
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assign pll_write_clk_pre_phy_clk = pll_write_clk;
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assign pll_write_clk_pre_phy_clk = pll_write_clk;
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endmodule
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endmodule
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