// (C) 2001-2017 Intel Corporation. All rights reserved.
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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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module ulight_fifo_hps_0_hps_io_border(
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module ulight_fifo_hps_0_hps_io_border(
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// memory
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// memory
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output wire [13 - 1 : 0 ] mem_a
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output wire [13 - 1 : 0 ] mem_a
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,output wire [3 - 1 : 0 ] mem_ba
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,output wire [3 - 1 : 0 ] mem_ba
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,output wire [1 - 1 : 0 ] mem_ck
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,output wire [1 - 1 : 0 ] mem_ck
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,output wire [1 - 1 : 0 ] mem_ck_n
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,output wire [1 - 1 : 0 ] mem_ck_n
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,output wire [1 - 1 : 0 ] mem_cke
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,output wire [1 - 1 : 0 ] mem_cke
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,output wire [1 - 1 : 0 ] mem_cs_n
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,output wire [1 - 1 : 0 ] mem_cs_n
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,output wire [1 - 1 : 0 ] mem_ras_n
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,output wire [1 - 1 : 0 ] mem_ras_n
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,output wire [1 - 1 : 0 ] mem_cas_n
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,output wire [1 - 1 : 0 ] mem_cas_n
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,output wire [1 - 1 : 0 ] mem_we_n
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,output wire [1 - 1 : 0 ] mem_we_n
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,output wire [1 - 1 : 0 ] mem_reset_n
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,output wire [1 - 1 : 0 ] mem_reset_n
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,inout wire [8 - 1 : 0 ] mem_dq
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,inout wire [8 - 1 : 0 ] mem_dq
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,inout wire [1 - 1 : 0 ] mem_dqs
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,inout wire [1 - 1 : 0 ] mem_dqs
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,inout wire [1 - 1 : 0 ] mem_dqs_n
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,inout wire [1 - 1 : 0 ] mem_dqs_n
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,output wire [1 - 1 : 0 ] mem_odt
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,output wire [1 - 1 : 0 ] mem_odt
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,output wire [1 - 1 : 0 ] mem_dm
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,output wire [1 - 1 : 0 ] mem_dm
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,input wire [1 - 1 : 0 ] oct_rzqin
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,input wire [1 - 1 : 0 ] oct_rzqin
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);
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);
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hps_sdram hps_sdram_inst(
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hps_sdram hps_sdram_inst(
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.mem_dq({
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.mem_dq({
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mem_dq[7:0] // 7:0
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mem_dq[7:0] // 7:0
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})
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})
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,.mem_odt({
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,.mem_odt({
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mem_odt[0:0] // 0:0
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mem_odt[0:0] // 0:0
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})
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})
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,.mem_ras_n({
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,.mem_ras_n({
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mem_ras_n[0:0] // 0:0
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mem_ras_n[0:0] // 0:0
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})
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})
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,.mem_dqs_n({
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,.mem_dqs_n({
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mem_dqs_n[0:0] // 0:0
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mem_dqs_n[0:0] // 0:0
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})
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})
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,.mem_dqs({
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,.mem_dqs({
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mem_dqs[0:0] // 0:0
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mem_dqs[0:0] // 0:0
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})
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})
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,.mem_dm({
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,.mem_dm({
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mem_dm[0:0] // 0:0
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mem_dm[0:0] // 0:0
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})
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})
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,.mem_we_n({
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,.mem_we_n({
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mem_we_n[0:0] // 0:0
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mem_we_n[0:0] // 0:0
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})
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})
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,.mem_cas_n({
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,.mem_cas_n({
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mem_cas_n[0:0] // 0:0
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mem_cas_n[0:0] // 0:0
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})
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})
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,.mem_ba({
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,.mem_ba({
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mem_ba[2:0] // 2:0
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mem_ba[2:0] // 2:0
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})
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})
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,.mem_a({
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,.mem_a({
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mem_a[12:0] // 12:0
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mem_a[12:0] // 12:0
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})
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})
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,.mem_cs_n({
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,.mem_cs_n({
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mem_cs_n[0:0] // 0:0
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mem_cs_n[0:0] // 0:0
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})
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})
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,.mem_ck({
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,.mem_ck({
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mem_ck[0:0] // 0:0
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mem_ck[0:0] // 0:0
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})
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})
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,.mem_cke({
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,.mem_cke({
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mem_cke[0:0] // 0:0
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mem_cke[0:0] // 0:0
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})
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})
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,.oct_rzqin({
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,.oct_rzqin({
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oct_rzqin[0:0] // 0:0
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oct_rzqin[0:0] // 0:0
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})
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})
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,.mem_reset_n({
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,.mem_reset_n({
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mem_reset_n[0:0] // 0:0
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mem_reset_n[0:0] // 0:0
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})
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})
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,.mem_ck_n({
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,.mem_ck_n({
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mem_ck_n[0:0] // 0:0
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mem_ck_n[0:0] // 0:0
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})
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})
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);
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);
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endmodule
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endmodule
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