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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [ulight_fifo_mm_interconnect_0.v] - Diff between revs 32 and 40

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// ulight_fifo_mm_interconnect_0.v
// ulight_fifo_mm_interconnect_0.v
 
 
// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// will probably be lost.
// 
// 
// Generated using ACDS version 17.0 598
// Generated using ACDS version 17.1 593
 
 
`timescale 1 ps / 1 ps
`timescale 1 ps / 1 ps
module ulight_fifo_mm_interconnect_0 (
module ulight_fifo_mm_interconnect_0 (
                input  wire [11:0] hps_0_h2f_axi_master_awid,                                        //                                       hps_0_h2f_axi_master.awid
                input  wire [11:0] hps_0_h2f_axi_master_awid,                                        //                                       hps_0_h2f_axi_master.awid
                input  wire [29:0] hps_0_h2f_axi_master_awaddr,                                      //                                                           .awaddr
                input  wire [29:0] hps_0_h2f_axi_master_awaddr,                                      //                                                           .awaddr

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