// (C) 2001-2017 Intel Corporation. All rights reserved.
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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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// Your use of Altera Corporation's design tools, logic functions and other
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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// $Id: //acds/rel/17.0std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
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// $Id: //acds/rel/17.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
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// $Revision: #1 $
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// $Revision: #1 $
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// $Date: 2017/01/22 $
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// $Date: 2017/07/30 $
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// $Author: swbranch $
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// $Author: swbranch $
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// -------------------------------------------------------
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// -------------------------------------------------------
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// Merlin Router
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// Merlin Router
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//
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//
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// Asserts the appropriate one-hot encoded channel based on
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// Asserts the appropriate one-hot encoded channel based on
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// either (a) the address or (b) the dest id. The DECODER_TYPE
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// either (a) the address or (b) the dest id. The DECODER_TYPE
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// parameter controls this behaviour. 0 means address decoder,
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// parameter controls this behaviour. 0 means address decoder,
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// 1 means dest id decoder.
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// 1 means dest id decoder.
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//
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//
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// In the case of (a), it also sets the destination id.
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// In the case of (a), it also sets the destination id.
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// -------------------------------------------------------
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// -------------------------------------------------------
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`timescale 1 ns / 1 ns
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`timescale 1 ns / 1 ns
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module ulight_fifo_mm_interconnect_0_router_002_default_decode
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module ulight_fifo_mm_interconnect_0_router_002_default_decode
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#(
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#(
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parameter DEFAULT_CHANNEL = -1,
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parameter DEFAULT_CHANNEL = -1,
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DEFAULT_WR_CHANNEL = 0,
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DEFAULT_WR_CHANNEL = 0,
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DEFAULT_RD_CHANNEL = 1,
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DEFAULT_RD_CHANNEL = 1,
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DEFAULT_DESTID = 0
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DEFAULT_DESTID = 0
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)
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)
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(output [104 - 100 : 0] default_destination_id,
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(output [104 - 100 : 0] default_destination_id,
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output [22-1 : 0] default_wr_channel,
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output [22-1 : 0] default_wr_channel,
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output [22-1 : 0] default_rd_channel,
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output [22-1 : 0] default_rd_channel,
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output [22-1 : 0] default_src_channel
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output [22-1 : 0] default_src_channel
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);
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);
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assign default_destination_id =
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assign default_destination_id =
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DEFAULT_DESTID[104 - 100 : 0];
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DEFAULT_DESTID[104 - 100 : 0];
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generate
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generate
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if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
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if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
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assign default_src_channel = '0;
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assign default_src_channel = '0;
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end
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end
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else begin : default_channel_assignment
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else begin : default_channel_assignment
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assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
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assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
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end
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end
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endgenerate
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endgenerate
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generate
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generate
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if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
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if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
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assign default_wr_channel = '0;
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assign default_wr_channel = '0;
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assign default_rd_channel = '0;
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assign default_rd_channel = '0;
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end
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end
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else begin : default_rw_channel_assignment
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else begin : default_rw_channel_assignment
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assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
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assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
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assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
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assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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module ulight_fifo_mm_interconnect_0_router_002
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module ulight_fifo_mm_interconnect_0_router_002
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(
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(
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// -------------------
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// -------------------
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// Clock & Reset
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// Clock & Reset
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// -------------------
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// -------------------
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input clk,
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input clk,
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input reset,
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input reset,
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// -------------------
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// -------------------
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// Command Sink (Input)
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// Command Sink (Input)
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// -------------------
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// -------------------
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input sink_valid,
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input sink_valid,
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input [129-1 : 0] sink_data,
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input [129-1 : 0] sink_data,
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input sink_startofpacket,
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input sink_startofpacket,
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input sink_endofpacket,
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input sink_endofpacket,
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output sink_ready,
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output sink_ready,
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// -------------------
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// -------------------
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// Command Source (Output)
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// Command Source (Output)
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// -------------------
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// -------------------
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output src_valid,
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output src_valid,
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output reg [129-1 : 0] src_data,
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output reg [129-1 : 0] src_data,
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output reg [22-1 : 0] src_channel,
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output reg [22-1 : 0] src_channel,
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output src_startofpacket,
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output src_startofpacket,
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output src_endofpacket,
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output src_endofpacket,
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input src_ready
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input src_ready
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);
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);
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// -------------------------------------------------------
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// -------------------------------------------------------
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// Local parameters and variables
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// Local parameters and variables
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// -------------------------------------------------------
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// -------------------------------------------------------
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localparam PKT_ADDR_H = 65;
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localparam PKT_ADDR_H = 65;
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localparam PKT_ADDR_L = 36;
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localparam PKT_ADDR_L = 36;
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localparam PKT_DEST_ID_H = 104;
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localparam PKT_DEST_ID_H = 104;
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localparam PKT_DEST_ID_L = 100;
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localparam PKT_DEST_ID_L = 100;
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localparam PKT_PROTECTION_H = 119;
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localparam PKT_PROTECTION_H = 119;
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localparam PKT_PROTECTION_L = 117;
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localparam PKT_PROTECTION_L = 117;
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localparam ST_DATA_W = 129;
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localparam ST_DATA_W = 129;
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localparam ST_CHANNEL_W = 22;
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localparam ST_CHANNEL_W = 22;
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localparam DECODER_TYPE = 1;
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localparam DECODER_TYPE = 1;
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localparam PKT_TRANS_WRITE = 68;
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localparam PKT_TRANS_WRITE = 68;
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localparam PKT_TRANS_READ = 69;
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localparam PKT_TRANS_READ = 69;
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localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
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localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
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localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
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localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
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// -------------------------------------------------------
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// -------------------------------------------------------
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// Figure out the number of bits to mask off for each slave span
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// Figure out the number of bits to mask off for each slave span
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// during address decoding
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// during address decoding
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// -------------------------------------------------------
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// -------------------------------------------------------
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// -------------------------------------------------------
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// -------------------------------------------------------
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// Work out which address bits are significant based on the
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// Work out which address bits are significant based on the
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// address range of the slaves. If the required width is too
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// address range of the slaves. If the required width is too
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// large or too small, we use the address field width instead.
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// large or too small, we use the address field width instead.
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// -------------------------------------------------------
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// -------------------------------------------------------
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localparam ADDR_RANGE = 64'h0;
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localparam ADDR_RANGE = 64'h0;
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localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
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localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
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localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
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localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
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(RANGE_ADDR_WIDTH == 0) ?
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(RANGE_ADDR_WIDTH == 0) ?
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PKT_ADDR_H :
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PKT_ADDR_H :
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PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
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PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
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localparam RG = RANGE_ADDR_WIDTH;
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localparam RG = RANGE_ADDR_WIDTH;
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localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
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localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
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reg [PKT_DEST_ID_W-1 : 0] destid;
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reg [PKT_DEST_ID_W-1 : 0] destid;
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// -------------------------------------------------------
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// -------------------------------------------------------
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// Pass almost everything through, untouched
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// Pass almost everything through, untouched
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// -------------------------------------------------------
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// -------------------------------------------------------
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assign sink_ready = src_ready;
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assign sink_ready = src_ready;
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assign src_valid = sink_valid;
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assign src_valid = sink_valid;
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assign src_startofpacket = sink_startofpacket;
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assign src_startofpacket = sink_startofpacket;
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assign src_endofpacket = sink_endofpacket;
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assign src_endofpacket = sink_endofpacket;
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wire [22-1 : 0] default_rd_channel;
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wire [22-1 : 0] default_rd_channel;
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wire [22-1 : 0] default_wr_channel;
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wire [22-1 : 0] default_wr_channel;
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// -------------------------------------------------------
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// -------------------------------------------------------
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// Write and read transaction signals
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// Write and read transaction signals
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// -------------------------------------------------------
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// -------------------------------------------------------
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wire write_transaction;
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wire write_transaction;
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assign write_transaction = sink_data[PKT_TRANS_WRITE];
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assign write_transaction = sink_data[PKT_TRANS_WRITE];
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wire read_transaction;
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wire read_transaction;
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assign read_transaction = sink_data[PKT_TRANS_READ];
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assign read_transaction = sink_data[PKT_TRANS_READ];
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ulight_fifo_mm_interconnect_0_router_002_default_decode the_default_decode(
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ulight_fifo_mm_interconnect_0_router_002_default_decode the_default_decode(
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.default_destination_id (),
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.default_destination_id (),
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.default_wr_channel (default_wr_channel),
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.default_wr_channel (default_wr_channel),
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.default_rd_channel (default_rd_channel),
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.default_rd_channel (default_rd_channel),
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.default_src_channel ()
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.default_src_channel ()
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);
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);
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always @* begin
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always @* begin
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src_data = sink_data;
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src_data = sink_data;
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src_channel = write_transaction ? default_wr_channel : default_rd_channel;
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src_channel = write_transaction ? default_wr_channel : default_rd_channel;
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// --------------------------------------------------
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// --------------------------------------------------
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// DestinationID Decoder
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// DestinationID Decoder
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// Sets the channel based on the destination ID.
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// Sets the channel based on the destination ID.
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// --------------------------------------------------
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// --------------------------------------------------
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destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
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destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
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if (destid == 0 && write_transaction) begin
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if (destid == 0 && write_transaction) begin
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src_channel = 22'b01;
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src_channel = 22'b01;
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end
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end
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if (destid == 0 && read_transaction) begin
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if (destid == 0 && read_transaction) begin
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src_channel = 22'b10;
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src_channel = 22'b10;
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end
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end
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end
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end
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// --------------------------------------------------
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// --------------------------------------------------
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// Ceil(log2()) function
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// Ceil(log2()) function
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// --------------------------------------------------
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// --------------------------------------------------
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function integer log2ceil;
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function integer log2ceil;
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input reg[65:0] val;
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input reg[65:0] val;
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reg [65:0] i;
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reg [65:0] i;
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begin
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begin
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i = 1;
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i = 1;
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log2ceil = 0;
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log2ceil = 0;
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while (i < val) begin
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while (i < val) begin
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log2ceil = log2ceil + 1;
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log2ceil = log2ceil + 1;
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i = i << 1;
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i = i << 1;
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end
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end
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end
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end
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endfunction
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endfunction
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endmodule
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endmodule
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