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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [ulight_fifo_mm_interconnect_0_rsp_mux.sv] - Diff between revs 32 and 40

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// (C) 2001-2017 Intel Corporation. All rights reserved.
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors.  Please refer to the applicable
// Intel or its authorized distributors.  Please refer to the applicable
// agreement for further details.
// agreement for further details.
 
 
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// sole purpose of programming logic devices manufactured by Altera and sold by
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors.  Please refer to the applicable
// Altera or its authorized distributors.  Please refer to the applicable
// agreement for further details.
// agreement for further details.
 
 
 
 
// $Id: //acds/rel/17.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
// $Id: //acds/rel/17.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
// $Revision: #1 $
// $Revision: #1 $
// $Date: 2017/01/22 $
// $Date: 2017/07/30 $
// $Author: swbranch $
// $Author: swbranch $
 
 
// ------------------------------------------
// ------------------------------------------
// Merlin Multiplexer
// Merlin Multiplexer
// ------------------------------------------
// ------------------------------------------

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