| Line 1... |
Line 1... |
|
|
|
|
|
|
|
|
|
|
|
|
com.altera.sopcmodel.ensemble.EClockAdapter
|
com.altera.sopcmodel.ensemble.EClockAdapter
|
HANDSHAKE
|
HANDSHAKE
|
false
|
false
|
| Line 51... |
Line 51... |
false
|
false
|
true
|
true
|
|
|
|
|
int
|
int
|
1502975928
|
1516735843
|
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
| Line 148... |
Line 148... |
true
|
true
|
|
|
|
|
name="auto_start"
|
name="auto_start"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="auto_start">
|
path="auto_start">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 406... |
Line 406... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 467... |
Line 467... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 512... |
Line 512... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 877... |
Line 877... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 923... |
Line 923... |
1
|
1
|
export
|
export
|
|
|
|
|
|
|
|
|
|
the requested settings for a module instance. -->
|
|
|
long
|
long
|
50000000
|
50000000
|
| Line 976... |
Line 976... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
qsys.ui.export_name
|
qsys.ui.export_name
|
| Line 1041... |
Line 1041... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
qsys.ui.export_name
|
qsys.ui.export_name
|
| Line 1090... |
Line 1090... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 1166... |
Line 1166... |
clk
|
clk
|
led_pio_test.clk
|
led_pio_test.clk
|
|
|
|
|
false
|
false
|
timecode_rx
|
|
clk
|
|
timecode_rx.clk
|
|
|
|
|
|
false
|
|
timecode_ready_rx
|
timecode_ready_rx
|
clk
|
clk
|
timecode_ready_rx.clk
|
timecode_ready_rx.clk
|
|
|
|
|
false
|
false
|
data_flag_rx
|
fifo_empty_rx_status
|
clk
|
clk
|
data_flag_rx.clk
|
fifo_empty_rx_status.clk
|
|
|
|
|
false
|
false
|
data_read_en_rx
|
link_start
|
clk
|
clk
|
data_read_en_rx.clk
|
link_start.clk
|
|
|
|
|
false
|
false
|
fifo_full_rx_status
|
write_en_tx
|
clk
|
clk
|
fifo_full_rx_status.clk
|
write_en_tx.clk
|
|
|
|
|
false
|
false
|
fifo_empty_rx_status
|
clock_sel
|
clk
|
clk
|
fifo_empty_rx_status.clk
|
clock_sel.clk
|
|
|
|
|
false
|
false
|
link_start
|
link_disable
|
clk
|
clk
|
link_start.clk
|
link_disable.clk
|
|
|
|
|
false
|
false
|
auto_start
|
auto_start
|
clk
|
clk
|
auto_start.clk
|
auto_start.clk
|
|
|
|
|
false
|
false
|
link_disable
|
timecode_tx_data
|
clk
|
clk
|
link_disable.clk
|
timecode_tx_data.clk
|
|
|
|
|
false
|
false
|
write_data_fifo_tx
|
data_info
|
clk
|
clk
|
write_data_fifo_tx.clk
|
data_info.clk
|
|
|
|
|
false
|
false
|
write_en_tx
|
timecode_tx_ready
|
clk
|
clk
|
write_en_tx.clk
|
timecode_tx_ready.clk
|
|
|
|
|
false
|
false
|
fifo_full_tx_status
|
fsm_info
|
clk
|
clk
|
fifo_full_tx_status.clk
|
fsm_info.clk
|
|
|
|
|
false
|
false
|
fifo_empty_tx_status
|
counter_tx_fifo
|
clk
|
clk
|
fifo_empty_tx_status.clk
|
counter_tx_fifo.clk
|
|
|
|
|
false
|
false
|
timecode_tx_data
|
counter_rx_fifo
|
clk
|
clk
|
timecode_tx_data.clk
|
counter_rx_fifo.clk
|
|
|
|
|
|
false
|
|
write_data_fifo_tx
|
|
clk
|
|
write_data_fifo_tx.clk
|
|
|
|
|
false
|
false
|
timecode_tx_enable
|
timecode_tx_enable
|
clk
|
clk
|
timecode_tx_enable.clk
|
timecode_tx_enable.clk
|
|
|
|
|
false
|
false
|
timecode_tx_ready
|
fifo_full_tx_status
|
clk
|
clk
|
timecode_tx_ready.clk
|
fifo_full_tx_status.clk
|
|
|
|
|
false
|
false
|
data_info
|
fifo_full_rx_status
|
clk
|
clk
|
data_info.clk
|
fifo_full_rx_status.clk
|
|
|
|
|
false
|
false
|
clock_sel
|
data_read_en_rx
|
clk
|
clk
|
clock_sel.clk
|
data_read_en_rx.clk
|
|
|
|
|
false
|
false
|
fsm_info
|
fifo_empty_tx_status
|
clk
|
clk
|
fsm_info.clk
|
fifo_empty_tx_status.clk
|
|
|
|
|
false
|
false
|
counter_tx_fifo
|
timecode_rx
|
clk
|
clk
|
counter_tx_fifo.clk
|
timecode_rx.clk
|
|
|
|
|
false
|
false
|
counter_rx_fifo
|
data_flag_rx
|
clk
|
clk
|
counter_rx_fifo.clk
|
data_flag_rx.clk
|
|
|
|
|
false
|
false
|
hps_0_fpga_interfaces
|
hps_0_fpga_interfaces
|
h2f_axi_clock
|
h2f_axi_clock
|
| Line 1327... |
Line 1327... |
rst_controller_001
|
rst_controller_001
|
clk
|
clk
|
rst_controller_001.clk
|
rst_controller_001.clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 1392... |
Line 1392... |
|
|
|
|
|
|
name="clock_sel"
|
name="clock_sel"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="clock_sel">
|
path="clock_sel">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 1650... |
Line 1650... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 1711... |
Line 1711... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 1756... |
Line 1756... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 2121... |
Line 2121... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 2170... |
Line 2170... |
|
|
|
|
|
|
name="counter_rx_fifo"
|
name="counter_rx_fifo"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="counter_rx_fifo">
|
path="counter_rx_fifo">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 2428... |
Line 2428... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 2489... |
Line 2489... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 2534... |
Line 2534... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 2881... |
Line 2881... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 2930... |
Line 2930... |
|
|
|
|
|
|
name="counter_tx_fifo"
|
name="counter_tx_fifo"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="counter_tx_fifo">
|
path="counter_tx_fifo">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 3188... |
Line 3188... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 3249... |
Line 3249... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 3294... |
Line 3294... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 3641... |
Line 3641... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 3690... |
Line 3690... |
|
|
|
|
|
|
name="data_flag_rx"
|
name="data_flag_rx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="data_flag_rx">
|
path="data_flag_rx">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 3948... |
Line 3948... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 4009... |
Line 4009... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 4054... |
Line 4054... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 4401... |
Line 4401... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 4450... |
Line 4450... |
|
|
|
|
|
|
name="data_info"
|
name="data_info"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="data_info">
|
path="data_info">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 4708... |
Line 4708... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 4769... |
Line 4769... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 4814... |
Line 4814... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 5161... |
Line 5161... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 5210... |
Line 5210... |
|
|
|
|
|
|
name="data_read_en_rx"
|
name="data_read_en_rx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="data_read_en_rx">
|
path="data_read_en_rx">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 5468... |
Line 5468... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 5529... |
Line 5529... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 5574... |
Line 5574... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 5939... |
Line 5939... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 5988... |
Line 5988... |
|
|
|
|
|
|
name="fifo_empty_rx_status"
|
name="fifo_empty_rx_status"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="fifo_empty_rx_status">
|
path="fifo_empty_rx_status">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 6246... |
Line 6246... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 6307... |
Line 6307... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 6352... |
Line 6352... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 6699... |
Line 6699... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 6748... |
Line 6748... |
|
|
|
|
|
|
name="fifo_empty_tx_status"
|
name="fifo_empty_tx_status"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="fifo_empty_tx_status">
|
path="fifo_empty_tx_status">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 7006... |
Line 7006... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 7067... |
Line 7067... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 7112... |
Line 7112... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 7459... |
Line 7459... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 7508... |
Line 7508... |
|
|
|
|
|
|
name="fifo_full_rx_status"
|
name="fifo_full_rx_status"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="fifo_full_rx_status">
|
path="fifo_full_rx_status">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 7766... |
Line 7766... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 7827... |
Line 7827... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 7872... |
Line 7872... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 8219... |
Line 8219... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 8268... |
Line 8268... |
|
|
|
|
|
|
name="fifo_full_tx_status"
|
name="fifo_full_tx_status"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="fifo_full_tx_status">
|
path="fifo_full_tx_status">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 8526... |
Line 8526... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 8587... |
Line 8587... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 8632... |
Line 8632... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 8979... |
Line 8979... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 9028... |
Line 9028... |
|
|
|
|
|
|
name="fsm_info"
|
name="fsm_info"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="fsm_info">
|
path="fsm_info">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 9286... |
Line 9286... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 9347... |
Line 9347... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 9392... |
Line 9392... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 9739... |
Line 9739... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 9785... |
Line 9785... |
6
|
6
|
export
|
export
|
|
|
|
|
|
|
|
|
|
the requested settings for a module instance. -->
|
|
|
postgeneration.simulation.init_file.param_name
|
postgeneration.simulation.init_file.param_name
|
ABS_RAM_MEM_INIT_FILENAME
|
ABS_RAM_MEM_INIT_FILENAME
|
| Line 17062... |
Line 17062... |
false
|
false
|
true
|
true
|
|
|
|
|
int
|
int
|
170
|
171
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
| Line 21471... |
Line 21471... |
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
25.0
|
50.0
|
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
25000000
|
50000000
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
25.0
|
50.0
|
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
25000000
|
50000000
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
| Line 21971... |
Line 21971... |
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
73
|
36
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
| Line 22067... |
Line 22067... |
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
1600000000
|
-1094967296
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
1600.0
|
-1094.967296
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
| Line 22163... |
Line 22163... |
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
25000000
|
50000000
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
25.0
|
50.0
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
| Line 22307... |
Line 22307... |
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
25000000
|
50000000
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
25.0
|
50.0
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
12500000
|
25000000
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
12.5
|
25.0
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
25000000
|
50000000
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
25.0
|
50.0
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
25000000
|
50000000
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
25.0
|
50.0
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
| Line 22403... |
Line 22403... |
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
39
|
19
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
| Line 22499... |
Line 22499... |
true
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
1000000000
|
2000000000
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
1000.0
|
2000.0
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
| Line 24463... |
Line 24463... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 24524... |
Line 24524... |
Output
|
Output
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 24585... |
Line 24585... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 24904... |
Line 24904... |
mm_interconnect_0.hps_0_h2f_axi_master
|
mm_interconnect_0.hps_0_h2f_axi_master
|
0
|
0
|
1073741824
|
1073741824
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
qsys.ui.export_name
|
qsys.ui.export_name
|
| Line 25051... |
Line 25051... |
|
|
|
|
|
|
name="hps_0_fpga_interfaces"
|
name="hps_0_fpga_interfaces"
|
kind="altera_interface_generator"
|
kind="altera_interface_generator"
|
version="17.0"
|
version="17.1"
|
path="hps_0.fpga_interfaces">
|
path="hps_0.fpga_interfaces">
|
|
the requested settings for a module instance. -->
|
|
|
postgeneration.simulation.init_file.param_name
|
postgeneration.simulation.init_file.param_name
|
| Line 36737... |
Line 36737... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 36798... |
Line 36798... |
Output
|
Output
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 36843... |
Line 36843... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 37166... |
Line 37166... |
|
|
|
|
|
|
name="hps_0_hps_io"
|
name="hps_0_hps_io"
|
kind="altera_hps_io"
|
kind="altera_hps_io"
|
version="17.0"
|
version="17.1"
|
path="hps_0.hps_io">
|
path="hps_0.hps_io">
|
|
the requested settings for a module instance. -->
|
|
|
postgeneration.simulation.init_file.param_name
|
postgeneration.simulation.init_file.param_name
|
| Line 37188... |
Line 37188... |
true
|
true
|
true
|
true
|
|
|
|
|
java.lang.String
|
java.lang.String
|
AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 2.5 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 100000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 8 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 1 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 5 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA4U23C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 13 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 16 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 120 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.6 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 24 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {2500 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 3333.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 26 PLL_WRITE_CLK_PHASE_PS_CACHE 2500 UART0_PinMuxing Unused sdmmc_clk_hz 1953125 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_12 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode N/A NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 3.333 PLL_AFI_CLK_MULT_CACHE 24 PLL_ADDR_CMD_CLK_DIV 10 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 511 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {3334 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 24 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 300.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {50010 ps} PLL_AFI_CLK_DIV 10 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 15.0 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 300.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 10 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.0 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.02 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 6.25 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 2500 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 175 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {125.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.6 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 5 TIMING_TIH 250 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 4 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing Unused desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 6250000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_6 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 2500 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 1.953125 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 50 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 5 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 125 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {3334 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 17 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 24 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 16 PLL_AFI_PHY_CLK_FREQ 300.0 periph_nand_sdmmc_clk_mhz 1.953125 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000000 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 1 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {300.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode N/A IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 6250000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN -0.01 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 6250000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 40.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 10 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {3334 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED false TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode N/A S2FCLK_USER0CLK_FREQ_HZ 100000000 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 400.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 511 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 2 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 2500 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 6 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 8 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode N/A hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 100.0 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM {ODT Disabled} AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 8000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_5 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 15.0 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 2 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.01 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 8.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_16_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 10 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 300.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_5 MR2_RTT_WR 0 MEM_TCL 7 GPIO_Pin_Used_DERIVED false JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 23 USE_2X_FF false ENUM_MEM_IF_TRC TRC_17 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 22 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 488281 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable false desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 1 F2SDRAM_Width {} dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 300.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.225 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_800_5_5_5 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 300.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 60.0 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {3334 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 511 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 4 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {2500 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 12 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 1.953125 PLL_AFI_HALF_CLK_MULT_CACHE 24 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 24 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 300.0 AFI_WRITE_DQS_WIDTH 1 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 6.25 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.01 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 8 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 1.953125 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.35 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {2500 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {3334 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 13 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {2500 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0001011001000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/6 MEM_IF_DM_WIDTH 1 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.5 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 8 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 24 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 37.5 DELAY_PER_OPA_TAP 416 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing Unused MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {3334 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 5000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_1 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 10 ENUM_MEM_IF_TCL TCL_7 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing Unused CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_3 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 1 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 100.0 MR2_CWL 1 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 170 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_8 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 6.25 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 2500 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 300.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 12 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 0 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 5 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP ODT_DISABLED MR0_BT 0 PLL_CONFIG_CLK_FREQ 20.0 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 0 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {300.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 24 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR {Dynamic ODT off} TIMING_TDQSCK 400 REF_CLK_FREQ_CACHE 125.0 AC_ROM_MR0_DLL_RESET 0001100110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_8 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {16670 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0001001001001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 8 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {300.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing Unused MEM_TREFI 2101 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 24 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED -0.01 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {3334 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 3 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 6 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_5 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 100 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.225 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {3334 ps} emac1_clk_mhz 1.953125 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 499 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 8 TIMING_BOARD_SKEW_WITHIN_DQS 0.02 ENUM_MEM_IF_TRAS TRAS_13 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 0 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.02 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 3 H2F_LW_AXI_CLOCK_FREQ 100 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {300.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 0 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {2500 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 6250000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 1953125 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 10 periph_base_clk_mhz 100.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_8 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 6 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.35 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing Unused INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 300.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 125.0 desired_cfg_clk_hz 100000000 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 10 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 1953125 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 1 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {6668 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 2 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 7 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 1953125 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 16777215 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0000000010000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode N/A quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 2101 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 2500 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {300.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 9 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 75.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY false ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 3 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 0 pin_muxing_check {Cyclone V+5CSEMA4U23C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 1953125 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 10 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 149700 PLL_WRITE_CLK_MULT_CACHE 24 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 300.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 1 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {2500 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 0.488281 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {}} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 6 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 300.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 2 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 8 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0000000001000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000000 TB_MEM_CLK_FREQ 300.0 AC_ROM_MR0 0001000110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 15000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 300.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {3334 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 6.25 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 1 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_2 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing Unused CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {6668 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode N/A ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.38 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 300.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 10 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 2500.0 S2FCLK_USER1CLK_Enable false SDIO_Mode N/A desired_qspi_clk_mhz 400.0 MEM_TRFC 23 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2
|
AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 2.5 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 100000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 8 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 1 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 2000.0 MEM_TRCD 5 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA4U23C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 13 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 50.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 16 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 120 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.6 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 24 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 50.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 50000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {2500 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 3333.0 periph_pll_vco_hz 2000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 26 PLL_WRITE_CLK_PHASE_PS_CACHE 2500 UART0_PinMuxing Unused sdmmc_clk_hz 1953125 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_12 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode N/A NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz -1094967296 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 3.333 PLL_AFI_CLK_MULT_CACHE 24 PLL_ADDR_CMD_CLK_DIV 10 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 511 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {3334 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 24 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 300.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {50010 ps} PLL_AFI_CLK_DIV 10 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 15.0 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 300.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 10 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.0 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.02 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 50000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 6.25 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 2500 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 175 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {125.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.6 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 5 TIMING_TIH 250 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 4 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing Unused desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 6250000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_6 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 2500 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 1.953125 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 50 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 5 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 125 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {3334 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 17 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 24 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 16 PLL_AFI_PHY_CLK_FREQ 300.0 periph_nand_sdmmc_clk_mhz 1.953125 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000000 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 1 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {300.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode N/A IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 6250000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN -0.01 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 6250000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 40.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 10 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {3334 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED false TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode N/A S2FCLK_USER0CLK_FREQ_HZ 100000000 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 400.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 511 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 2 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 2500 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 6 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 8 dbg_timer_clk_hz 50000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode N/A hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 100.0 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM {ODT Disabled} AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 8000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_5 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 15.0 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 2 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.01 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 8.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_16_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 10 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 300.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_5 MR2_RTT_WR 0 MEM_TCL 7 GPIO_Pin_Used_DERIVED false JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 23 USE_2X_FF false ENUM_MEM_IF_TRC TRC_17 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 22 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 488281 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable false desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 1 F2SDRAM_Width {} dbg_clk_hz 25000000 PLL_AFI_CLK_FREQ 300.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.225 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_800_5_5_5 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 300.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 60.0 dbg_timer_clk_mhz 50.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {3334 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 511 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 4 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {2500 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 12 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 1.953125 PLL_AFI_HALF_CLK_MULT_CACHE 24 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 24 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 300.0 AFI_WRITE_DQS_WIDTH 1 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 6.25 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 50000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.01 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 8 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 1.953125 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz -1094.967296 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.35 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {2500 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {3334 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 13 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {2500 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0001011001000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/6 MEM_IF_DM_WIDTH 1 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.5 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 8 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 24 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 37.5 DELAY_PER_OPA_TAP 416 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing Unused MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {3334 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 25.0 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 5000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_1 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 10 ENUM_MEM_IF_TCL TCL_7 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing Unused CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_3 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 1 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 100.0 MR2_CWL 1 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 171 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 19 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_8 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 6.25 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 2500 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 36 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 300.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 12 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 0 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 5 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP ODT_DISABLED MR0_BT 0 PLL_CONFIG_CLK_FREQ 20.0 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 0 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {300.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 24 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 50.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR {Dynamic ODT off} TIMING_TDQSCK 400 REF_CLK_FREQ_CACHE 125.0 AC_ROM_MR0_DLL_RESET 0001100110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_8 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {16670 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0001001001001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 8 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {300.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing Unused MEM_TREFI 2101 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 24 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 50.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED -0.01 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {3334 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 3 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 6 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_5 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 100 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.225 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {3334 ps} emac1_clk_mhz 1.953125 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 499 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 8 TIMING_BOARD_SKEW_WITHIN_DQS 0.02 ENUM_MEM_IF_TRAS TRAS_13 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 0 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.02 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 3 H2F_LW_AXI_CLOCK_FREQ 100 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {300.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 0 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {2500 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 6250000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 1953125 eosc2_clk_mhz 50.0 PLL_MEM_CLK_DIV_CACHE 10 periph_base_clk_mhz 100.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_8 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 6 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.35 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing Unused INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 300.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 125.0 desired_cfg_clk_hz 100000000 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 10 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 1953125 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 1 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {6668 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 2 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 7 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 1953125 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 16777215 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0000000010000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode N/A quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 2101 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 2500 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {300.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 9 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 75.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY false ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 3 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 0 pin_muxing_check {Cyclone V+5CSEMA4U23C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 1953125 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 10 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 149700 PLL_WRITE_CLK_MULT_CACHE 24 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 300.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 1 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {2500 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 0.488281 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {}} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 6 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 300.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 2 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 8 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0000000001000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000000 TB_MEM_CLK_FREQ 300.0 AC_ROM_MR0 0001000110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 15000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 300.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {3334 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 6.25 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 1 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_2 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing Unused CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 50000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {6668 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode N/A ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.38 dbg_base_clk_hz 50000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 300.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 10 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 2500.0 S2FCLK_USER1CLK_Enable false SDIO_Mode N/A desired_qspi_clk_mhz 400.0 MEM_TRFC 23 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2
|
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
| Line 48845... |
Line 48845... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 48984... |
Line 48984... |
|
|
|
|
|
|
name="led_pio_test"
|
name="led_pio_test"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="led_pio_test">
|
path="led_pio_test">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 49242... |
Line 49242... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 49303... |
Line 49303... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 49348... |
Line 49348... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 49713... |
Line 49713... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 49762... |
Line 49762... |
|
|
|
|
|
|
name="link_disable"
|
name="link_disable"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="link_disable">
|
path="link_disable">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 50020... |
Line 50020... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 50081... |
Line 50081... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 50126... |
Line 50126... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 50491... |
Line 50491... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 50540... |
Line 50540... |
|
|
|
|
|
|
name="link_start"
|
name="link_start"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="link_start">
|
path="link_start">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 50798... |
Line 50798... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 50859... |
Line 50859... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 50904... |
Line 50904... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 51269... |
Line 51269... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 51315... |
Line 51315... |
1
|
1
|
export
|
export
|
|
|
|
|
|
|
|
|
|
the requested settings for a module instance. -->
|
|
|
boolean
|
boolean
|
false
|
false
|
| Line 51354... |
Line 51354... |
true
|
true
|
DEVICE
|
DEVICE
|
|
|
|
|
java.lang.String
|
java.lang.String
|
1
|
2
|
false
|
false
|
false
|
false
|
true
|
true
|
true
|
true
|
|
|
| Line 51378... |
Line 51378... |
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
100.0
|
50.0
|
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
java.lang.String
|
java.lang.String
|
100.0 MHz
|
50.0 MHz
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
| Line 51402... |
Line 51402... |
false
|
false
|
true
|
true
|
|
|
|
|
java.lang.String
|
java.lang.String
|
direct
|
normal
|
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
java.lang.String
|
java.lang.String
|
Global Clock
|
Global Clock
|
false
|
false
|
true
|
true
|
false
|
true
|
true
|
true
|
|
|
|
|
int
|
int
|
32
|
32
|
| Line 51450... |
Line 51450... |
false
|
false
|
true
|
true
|
|
|
|
|
java.lang.String
|
java.lang.String
|
direct
|
normal
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
| Line 51546... |
Line 51546... |
false
|
false
|
true
|
true
|
|
|
|
|
int
|
int
|
4
|
8
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
| Line 51626... |
Line 51626... |
false
|
false
|
true
|
true
|
|
|
|
|
double
|
double
|
100.0
|
250.0
|
false
|
false
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
| Line 53754... |
Line 53754... |
false
|
false
|
true
|
true
|
|
|
|
|
int
|
int
|
2
|
4
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
|
|
int
|
int
|
2
|
4
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
| Line 54834... |
Line 54834... |
false
|
false
|
true
|
true
|
|
|
|
|
int
|
int
|
30
|
20
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
|
|
int
|
int
|
2000
|
4000
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
| Line 54866... |
Line 54866... |
false
|
false
|
true
|
true
|
|
|
|
|
java.lang.String
|
java.lang.String
|
none
|
gclk
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
| Line 54882... |
Line 54882... |
false
|
false
|
true
|
true
|
|
|
|
|
java.lang.String
|
java.lang.String
|
m_cnt
|
fb_1
|
true
|
true
|
true
|
true
|
false
|
false
|
true
|
true
|
|
|
| Line 54914... |
Line 54914... |
true
|
true
|
true
|
true
|
|
|
|
|
[Ljava.lang.String;
|
[Ljava.lang.String;
|
2,2,256,256,false,true,false,false,256,256,1,0,ph_mux_clk,true,false,2,30,2000,400.0 MHz,1,none,glb,m_cnt,ph_mux_clk,false
|
4,4,256,256,false,true,false,false,256,256,1,0,ph_mux_clk,true,false,2,20,4000,400.0 MHz,1,gclk,glb,fb_1,ph_mux_clk,false
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
| Line 55112... |
Line 55112... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 55157... |
Line 55157... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 55202... |
Line 55202... |
Input
|
Input
|
1
|
1
|
reset
|
reset
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 55271... |
Line 55271... |
Output
|
Output
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
ui.blockdiagram.direction
|
ui.blockdiagram.direction
|
| Line 55320... |
Line 55320... |
Output
|
Output
|
1
|
1
|
export
|
export
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
ui.blockdiagram.direction
|
ui.blockdiagram.direction
|
| Line 55373... |
Line 55373... |
|
|
|
|
|
|
name="timecode_ready_rx"
|
name="timecode_ready_rx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="timecode_ready_rx">
|
path="timecode_ready_rx">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 55631... |
Line 55631... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 55692... |
Line 55692... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 55737... |
Line 55737... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 56084... |
Line 56084... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 56133... |
Line 56133... |
|
|
|
|
|
|
name="timecode_rx"
|
name="timecode_rx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="timecode_rx">
|
path="timecode_rx">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 56391... |
Line 56391... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 56452... |
Line 56452... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 56497... |
Line 56497... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 56844... |
Line 56844... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 56893... |
Line 56893... |
|
|
|
|
|
|
name="timecode_tx_data"
|
name="timecode_tx_data"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="timecode_tx_data">
|
path="timecode_tx_data">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 57151... |
Line 57151... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 57212... |
Line 57212... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 57257... |
Line 57257... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 57622... |
Line 57622... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 57671... |
Line 57671... |
|
|
|
|
|
|
name="timecode_tx_enable"
|
name="timecode_tx_enable"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="timecode_tx_enable">
|
path="timecode_tx_enable">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 57929... |
Line 57929... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 57990... |
Line 57990... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 58035... |
Line 58035... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 58400... |
Line 58400... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 58449... |
Line 58449... |
|
|
|
|
|
|
name="timecode_tx_ready"
|
name="timecode_tx_ready"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="timecode_tx_ready">
|
path="timecode_tx_ready">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 58707... |
Line 58707... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 58768... |
Line 58768... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 58813... |
Line 58813... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 59160... |
Line 59160... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 59209... |
Line 59209... |
|
|
|
|
|
|
name="write_data_fifo_tx"
|
name="write_data_fifo_tx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="write_data_fifo_tx">
|
path="write_data_fifo_tx">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 59467... |
Line 59467... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 59528... |
Line 59528... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 59573... |
Line 59573... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 59938... |
Line 59938... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 59987... |
Line 59987... |
|
|
|
|
|
|
name="write_en_tx"
|
name="write_en_tx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
path="write_en_tx">
|
path="write_en_tx">
|
|
the requested settings for a module instance. -->
|
|
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
|
| Line 60245... |
Line 60245... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 60306... |
Line 60306... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 60351... |
Line 60351... |
Input
|
Input
|
1
|
1
|
reset_n
|
reset_n
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
embeddedsw.configuration.isFlash
|
embeddedsw.configuration.isFlash
|
| Line 60716... |
Line 60716... |
Output
|
Output
|
32
|
32
|
readdata
|
readdata
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 60765... |
Line 60765... |
|
|
|
|
|
|
name="mm_interconnect_0"
|
name="mm_interconnect_0"
|
kind="altera_mm_interconnect"
|
kind="altera_mm_interconnect"
|
version="17.0"
|
version="17.1"
|
path="mm_interconnect_0">
|
path="mm_interconnect_0">
|
|
the requested settings for a module instance. -->
|
|
|
interconnect_id.auto_start.s1
|
interconnect_id.auto_start.s1
|
| Line 61070... |
Line 61070... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
merlin.flow.read_cp
|
merlin.flow.read_cp
|
| Line 61413... |
Line 61413... |
Input
|
Input
|
1
|
1
|
rready
|
rready
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 61461... |
Line 61461... |
|
|
|
|
|
|
name="hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset"
|
name="hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset"
|
kind="reset_sink"
|
kind="reset_sink"
|
version="17.0">
|
version="17.1">
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 61509... |
Line 61509... |
|
|
|
|
|
|
name="led_pio_test_reset_reset_bridge_in_reset"
|
name="led_pio_test_reset_reset_bridge_in_reset"
|
kind="reset_sink"
|
kind="reset_sink"
|
version="17.0">
|
version="17.1">
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 61554... |
Line 61554... |
Input
|
Input
|
1
|
1
|
reset
|
reset
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 61855... |
Line 61855... |
auto_start.s1
|
auto_start.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 62156... |
Line 62156... |
clock_sel.s1
|
clock_sel.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 62439... |
Line 62439... |
counter_rx_fifo.s1
|
counter_rx_fifo.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 62722... |
Line 62722... |
counter_tx_fifo.s1
|
counter_tx_fifo.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 63005... |
Line 63005... |
data_flag_rx.s1
|
data_flag_rx.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 63288... |
Line 63288... |
data_info.s1
|
data_info.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 63589... |
Line 63589... |
data_read_en_rx.s1
|
data_read_en_rx.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 63872... |
Line 63872... |
fifo_empty_rx_status.s1
|
fifo_empty_rx_status.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 64155... |
Line 64155... |
fifo_empty_tx_status.s1
|
fifo_empty_tx_status.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 64438... |
Line 64438... |
fifo_full_rx_status.s1
|
fifo_full_rx_status.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 64721... |
Line 64721... |
fifo_full_tx_status.s1
|
fifo_full_tx_status.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 65004... |
Line 65004... |
fsm_info.s1
|
fsm_info.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 65305... |
Line 65305... |
led_pio_test.s1
|
led_pio_test.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 65606... |
Line 65606... |
link_disable.s1
|
link_disable.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 65907... |
Line 65907... |
link_start.s1
|
link_start.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 66190... |
Line 66190... |
timecode_ready_rx.s1
|
timecode_ready_rx.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 66473... |
Line 66473... |
timecode_rx.s1
|
timecode_rx.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 66774... |
Line 66774... |
timecode_tx_data.s1
|
timecode_tx_data.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 67075... |
Line 67075... |
timecode_tx_enable.s1
|
timecode_tx_enable.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 67358... |
Line 67358... |
timecode_tx_ready.s1
|
timecode_tx_ready.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 67659... |
Line 67659... |
write_data_fifo_tx.s1
|
write_data_fifo_tx.s1
|
0
|
0
|
16
|
16
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
com.altera.entityinterfaces.IConnectionPoint
|
com.altera.entityinterfaces.IConnectionPoint
|
| Line 67964... |
Line 67964... |
|
|
|
|
|
|
name="rst_controller"
|
name="rst_controller"
|
kind="altera_reset_controller"
|
kind="altera_reset_controller"
|
version="17.0"
|
version="17.1"
|
path="rst_controller">
|
path="rst_controller">
|
|
the requested settings for a module instance. -->
|
|
|
int
|
int
|
| Line 68184... |
Line 68184... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 68229... |
Line 68229... |
Input
|
Input
|
1
|
1
|
reset
|
reset
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 68274... |
Line 68274... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 68339... |
Line 68339... |
|
|
|
|
|
|
name="rst_controller_001"
|
name="rst_controller_001"
|
kind="altera_reset_controller"
|
kind="altera_reset_controller"
|
version="17.0"
|
version="17.1"
|
path="rst_controller_001">
|
path="rst_controller_001">
|
|
the requested settings for a module instance. -->
|
|
|
int
|
int
|
| Line 68559... |
Line 68559... |
false
|
false
|
true
|
true
|
true
|
true
|
true
|
true
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 68604... |
Line 68604... |
Input
|
Input
|
1
|
1
|
reset
|
reset
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
boolean
|
boolean
|
| Line 68649... |
Line 68649... |
Input
|
Input
|
1
|
1
|
clk
|
clk
|
|
|
|
|
|
|
|
parameters are a RESULT of the module parameters. -->
|
|
|
java.lang.String
|
java.lang.String
|
| Line 68714... |
Line 68714... |
|
|
|
|
|
|
name="clk_0.clk/led_pio_test.clk"
|
name="clk_0.clk/led_pio_test.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="led_pio_test.clk">
|
end="led_pio_test.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 68739... |
Line 68739... |
clk
|
clk
|
led_pio_test
|
led_pio_test
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/timecode_rx.clk"
|
name="clk_0.clk/timecode_ready_rx.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="timecode_rx.clk">
|
end="timecode_ready_rx.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 68762... |
Line 68762... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
timecode_rx
|
timecode_ready_rx
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/timecode_ready_rx.clk"
|
name="clk_0.clk/fifo_empty_rx_status.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="timecode_ready_rx.clk">
|
end="fifo_empty_rx_status.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 68789... |
Line 68789... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
timecode_ready_rx
|
fifo_empty_rx_status
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/data_flag_rx.clk"
|
name="clk_0.clk/link_start.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="data_flag_rx.clk">
|
end="link_start.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 68816... |
Line 68816... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
data_flag_rx
|
link_start
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/data_read_en_rx.clk"
|
name="clk_0.clk/write_en_tx.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="data_read_en_rx.clk">
|
end="write_en_tx.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 68843... |
Line 68843... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
data_read_en_rx
|
write_en_tx
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/fifo_full_rx_status.clk"
|
name="clk_0.clk/clock_sel.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="fifo_full_rx_status.clk">
|
end="clock_sel.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 68870... |
Line 68870... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
fifo_full_rx_status
|
clock_sel
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/fifo_empty_rx_status.clk"
|
name="clk_0.clk/link_disable.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="fifo_empty_rx_status.clk">
|
end="link_disable.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 68897... |
Line 68897... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
fifo_empty_rx_status
|
link_disable
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/link_start.clk"
|
name="clk_0.clk/auto_start.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="link_start.clk">
|
end="auto_start.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 68924... |
Line 68924... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
link_start
|
auto_start
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/auto_start.clk"
|
name="clk_0.clk/timecode_tx_data.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="auto_start.clk">
|
end="timecode_tx_data.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 68951... |
Line 68951... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
auto_start
|
timecode_tx_data
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/link_disable.clk"
|
name="clk_0.clk/data_info.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="link_disable.clk">
|
end="data_info.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 68978... |
Line 68978... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
link_disable
|
data_info
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/write_data_fifo_tx.clk"
|
name="clk_0.clk/timecode_tx_ready.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="write_data_fifo_tx.clk">
|
end="timecode_tx_ready.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69005... |
Line 69005... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
write_data_fifo_tx
|
timecode_tx_ready
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/write_en_tx.clk"
|
name="clk_0.clk/fsm_info.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="write_en_tx.clk">
|
end="fsm_info.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69032... |
Line 69032... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
write_en_tx
|
fsm_info
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/fifo_full_tx_status.clk"
|
name="clk_0.clk/counter_tx_fifo.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="fifo_full_tx_status.clk">
|
end="counter_tx_fifo.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69059... |
Line 69059... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
fifo_full_tx_status
|
counter_tx_fifo
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/fifo_empty_tx_status.clk"
|
name="clk_0.clk/counter_rx_fifo.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="fifo_empty_tx_status.clk">
|
end="counter_rx_fifo.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69086... |
Line 69086... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
fifo_empty_tx_status
|
counter_rx_fifo
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/timecode_tx_data.clk"
|
name="clk_0.clk/write_data_fifo_tx.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="timecode_tx_data.clk">
|
end="write_data_fifo_tx.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69113... |
Line 69113... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
timecode_tx_data
|
write_data_fifo_tx
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/timecode_tx_enable.clk"
|
name="clk_0.clk/timecode_tx_enable.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="timecode_tx_enable.clk">
|
end="timecode_tx_enable.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 69144... |
Line 69144... |
clk
|
clk
|
timecode_tx_enable
|
timecode_tx_enable
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/timecode_tx_ready.clk"
|
name="clk_0.clk/fifo_full_tx_status.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="timecode_tx_ready.clk">
|
end="fifo_full_tx_status.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69167... |
Line 69167... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
timecode_tx_ready
|
fifo_full_tx_status
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/data_info.clk"
|
name="clk_0.clk/fifo_full_rx_status.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="data_info.clk">
|
end="fifo_full_rx_status.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69194... |
Line 69194... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
data_info
|
fifo_full_rx_status
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/clock_sel.clk"
|
name="clk_0.clk/data_read_en_rx.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="clock_sel.clk">
|
end="data_read_en_rx.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69221... |
Line 69221... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
clock_sel
|
data_read_en_rx
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/fsm_info.clk"
|
name="clk_0.clk/fifo_empty_tx_status.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="fsm_info.clk">
|
end="fifo_empty_tx_status.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69248... |
Line 69248... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
fsm_info
|
fifo_empty_tx_status
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/counter_tx_fifo.clk"
|
name="clk_0.clk/timecode_rx.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="counter_tx_fifo.clk">
|
end="timecode_rx.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69275... |
Line 69275... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
counter_tx_fifo
|
timecode_rx
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/counter_rx_fifo.clk"
|
name="clk_0.clk/data_flag_rx.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="counter_rx_fifo.clk">
|
end="data_flag_rx.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
false
|
false
|
true
|
true
|
| Line 69302... |
Line 69302... |
true
|
true
|
true
|
true
|
|
|
clk_0
|
clk_0
|
clk
|
clk
|
counter_rx_fifo
|
data_flag_rx
|
clk
|
clk
|
|
|
|
|
name="clk_0.clk/hps_0_fpga_interfaces.h2f_axi_clock"
|
name="clk_0.clk/hps_0_fpga_interfaces.h2f_axi_clock"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="hps_0_fpga_interfaces.h2f_axi_clock">
|
end="hps_0_fpga_interfaces.h2f_axi_clock">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 69335... |
Line 69335... |
h2f_axi_clock
|
h2f_axi_clock
|
|
|
|
|
name="clk_0.clk/pll_0.refclk"
|
name="clk_0.clk/pll_0.refclk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="pll_0.refclk">
|
end="pll_0.refclk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 69362... |
Line 69362... |
refclk
|
refclk
|
|
|
|
|
name="clk_0.clk/pll_0.refclk1"
|
name="clk_0.clk/pll_0.refclk1"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="pll_0.refclk1">
|
end="pll_0.refclk1">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 69389... |
Line 69389... |
refclk1
|
refclk1
|
|
|
|
|
name="clk_0.clk_reset/pll_0.reset"
|
name="clk_0.clk_reset/pll_0.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="pll_0.reset">
|
end="pll_0.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 69416... |
Line 69416... |
reset
|
reset
|
|
|
|
|
name="hps_0_fpga_interfaces.h2f_axi_master/mm_interconnect_0.hps_0_h2f_axi_master"
|
name="hps_0_fpga_interfaces.h2f_axi_master/mm_interconnect_0.hps_0_h2f_axi_master"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0_fpga_interfaces.h2f_axi_master"
|
start="hps_0_fpga_interfaces.h2f_axi_master"
|
end="mm_interconnect_0.hps_0_h2f_axi_master">
|
end="mm_interconnect_0.hps_0_h2f_axi_master">
|
|
|
int
|
int
|
1
|
1
|
| Line 69467... |
Line 69467... |
hps_0_h2f_axi_master
|
hps_0_h2f_axi_master
|
|
|
|
|
name="clk_0.clk/mm_interconnect_0.clk_0_clk"
|
name="clk_0.clk/mm_interconnect_0.clk_0_clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="mm_interconnect_0.clk_0_clk">
|
end="mm_interconnect_0.clk_0_clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 69494... |
Line 69494... |
clk_0_clk
|
clk_0_clk
|
|
|
|
|
name="mm_interconnect_0.led_pio_test_s1/led_pio_test.s1"
|
name="mm_interconnect_0.led_pio_test_s1/led_pio_test.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.led_pio_test_s1"
|
start="mm_interconnect_0.led_pio_test_s1"
|
end="led_pio_test.s1">
|
end="led_pio_test.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 69545... |
Line 69545... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.timecode_rx_s1/timecode_rx.s1"
|
name="mm_interconnect_0.timecode_rx_s1/timecode_rx.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.timecode_rx_s1"
|
start="mm_interconnect_0.timecode_rx_s1"
|
end="timecode_rx.s1">
|
end="timecode_rx.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 69596... |
Line 69596... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.timecode_ready_rx_s1/timecode_ready_rx.s1"
|
name="mm_interconnect_0.timecode_ready_rx_s1/timecode_ready_rx.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.timecode_ready_rx_s1"
|
start="mm_interconnect_0.timecode_ready_rx_s1"
|
end="timecode_ready_rx.s1">
|
end="timecode_ready_rx.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 69647... |
Line 69647... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.data_flag_rx_s1/data_flag_rx.s1"
|
name="mm_interconnect_0.data_flag_rx_s1/data_flag_rx.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.data_flag_rx_s1"
|
start="mm_interconnect_0.data_flag_rx_s1"
|
end="data_flag_rx.s1">
|
end="data_flag_rx.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 69698... |
Line 69698... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.data_read_en_rx_s1/data_read_en_rx.s1"
|
name="mm_interconnect_0.data_read_en_rx_s1/data_read_en_rx.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.data_read_en_rx_s1"
|
start="mm_interconnect_0.data_read_en_rx_s1"
|
end="data_read_en_rx.s1">
|
end="data_read_en_rx.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 69749... |
Line 69749... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.fifo_full_rx_status_s1/fifo_full_rx_status.s1"
|
name="mm_interconnect_0.fifo_full_rx_status_s1/fifo_full_rx_status.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.fifo_full_rx_status_s1"
|
start="mm_interconnect_0.fifo_full_rx_status_s1"
|
end="fifo_full_rx_status.s1">
|
end="fifo_full_rx_status.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 69800... |
Line 69800... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.fifo_empty_rx_status_s1/fifo_empty_rx_status.s1"
|
name="mm_interconnect_0.fifo_empty_rx_status_s1/fifo_empty_rx_status.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.fifo_empty_rx_status_s1"
|
start="mm_interconnect_0.fifo_empty_rx_status_s1"
|
end="fifo_empty_rx_status.s1">
|
end="fifo_empty_rx_status.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 69851... |
Line 69851... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.link_start_s1/link_start.s1"
|
name="mm_interconnect_0.link_start_s1/link_start.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.link_start_s1"
|
start="mm_interconnect_0.link_start_s1"
|
end="link_start.s1">
|
end="link_start.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 69902... |
Line 69902... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.auto_start_s1/auto_start.s1"
|
name="mm_interconnect_0.auto_start_s1/auto_start.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.auto_start_s1"
|
start="mm_interconnect_0.auto_start_s1"
|
end="auto_start.s1">
|
end="auto_start.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 69953... |
Line 69953... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.link_disable_s1/link_disable.s1"
|
name="mm_interconnect_0.link_disable_s1/link_disable.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.link_disable_s1"
|
start="mm_interconnect_0.link_disable_s1"
|
end="link_disable.s1">
|
end="link_disable.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70004... |
Line 70004... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.write_data_fifo_tx_s1/write_data_fifo_tx.s1"
|
name="mm_interconnect_0.write_data_fifo_tx_s1/write_data_fifo_tx.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.write_data_fifo_tx_s1"
|
start="mm_interconnect_0.write_data_fifo_tx_s1"
|
end="write_data_fifo_tx.s1">
|
end="write_data_fifo_tx.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70055... |
Line 70055... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.write_en_tx_s1/write_en_tx.s1"
|
name="mm_interconnect_0.write_en_tx_s1/write_en_tx.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.write_en_tx_s1"
|
start="mm_interconnect_0.write_en_tx_s1"
|
end="write_en_tx.s1">
|
end="write_en_tx.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70106... |
Line 70106... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.fifo_full_tx_status_s1/fifo_full_tx_status.s1"
|
name="mm_interconnect_0.fifo_full_tx_status_s1/fifo_full_tx_status.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.fifo_full_tx_status_s1"
|
start="mm_interconnect_0.fifo_full_tx_status_s1"
|
end="fifo_full_tx_status.s1">
|
end="fifo_full_tx_status.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70157... |
Line 70157... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.fifo_empty_tx_status_s1/fifo_empty_tx_status.s1"
|
name="mm_interconnect_0.fifo_empty_tx_status_s1/fifo_empty_tx_status.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.fifo_empty_tx_status_s1"
|
start="mm_interconnect_0.fifo_empty_tx_status_s1"
|
end="fifo_empty_tx_status.s1">
|
end="fifo_empty_tx_status.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70208... |
Line 70208... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.timecode_tx_data_s1/timecode_tx_data.s1"
|
name="mm_interconnect_0.timecode_tx_data_s1/timecode_tx_data.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.timecode_tx_data_s1"
|
start="mm_interconnect_0.timecode_tx_data_s1"
|
end="timecode_tx_data.s1">
|
end="timecode_tx_data.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70259... |
Line 70259... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.timecode_tx_enable_s1/timecode_tx_enable.s1"
|
name="mm_interconnect_0.timecode_tx_enable_s1/timecode_tx_enable.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.timecode_tx_enable_s1"
|
start="mm_interconnect_0.timecode_tx_enable_s1"
|
end="timecode_tx_enable.s1">
|
end="timecode_tx_enable.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70310... |
Line 70310... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.timecode_tx_ready_s1/timecode_tx_ready.s1"
|
name="mm_interconnect_0.timecode_tx_ready_s1/timecode_tx_ready.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.timecode_tx_ready_s1"
|
start="mm_interconnect_0.timecode_tx_ready_s1"
|
end="timecode_tx_ready.s1">
|
end="timecode_tx_ready.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70361... |
Line 70361... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.data_info_s1/data_info.s1"
|
name="mm_interconnect_0.data_info_s1/data_info.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.data_info_s1"
|
start="mm_interconnect_0.data_info_s1"
|
end="data_info.s1">
|
end="data_info.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70412... |
Line 70412... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.clock_sel_s1/clock_sel.s1"
|
name="mm_interconnect_0.clock_sel_s1/clock_sel.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.clock_sel_s1"
|
start="mm_interconnect_0.clock_sel_s1"
|
end="clock_sel.s1">
|
end="clock_sel.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70463... |
Line 70463... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.fsm_info_s1/fsm_info.s1"
|
name="mm_interconnect_0.fsm_info_s1/fsm_info.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.fsm_info_s1"
|
start="mm_interconnect_0.fsm_info_s1"
|
end="fsm_info.s1">
|
end="fsm_info.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70514... |
Line 70514... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.counter_tx_fifo_s1/counter_tx_fifo.s1"
|
name="mm_interconnect_0.counter_tx_fifo_s1/counter_tx_fifo.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.counter_tx_fifo_s1"
|
start="mm_interconnect_0.counter_tx_fifo_s1"
|
end="counter_tx_fifo.s1">
|
end="counter_tx_fifo.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70565... |
Line 70565... |
s1
|
s1
|
|
|
|
|
name="mm_interconnect_0.counter_rx_fifo_s1/counter_rx_fifo.s1"
|
name="mm_interconnect_0.counter_rx_fifo_s1/counter_rx_fifo.s1"
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="mm_interconnect_0.counter_rx_fifo_s1"
|
start="mm_interconnect_0.counter_rx_fifo_s1"
|
end="counter_rx_fifo.s1">
|
end="counter_rx_fifo.s1">
|
|
|
int
|
int
|
1
|
1
|
| Line 70616... |
Line 70616... |
s1
|
s1
|
|
|
|
|
name="rst_controller.reset_out/auto_start.reset"
|
name="rst_controller.reset_out/auto_start.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="auto_start.reset">
|
end="auto_start.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70643... |
Line 70643... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/clock_sel.reset"
|
name="rst_controller.reset_out/clock_sel.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="clock_sel.reset">
|
end="clock_sel.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70670... |
Line 70670... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/counter_rx_fifo.reset"
|
name="rst_controller.reset_out/counter_rx_fifo.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="counter_rx_fifo.reset">
|
end="counter_rx_fifo.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70697... |
Line 70697... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/counter_tx_fifo.reset"
|
name="rst_controller.reset_out/counter_tx_fifo.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="counter_tx_fifo.reset">
|
end="counter_tx_fifo.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70724... |
Line 70724... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/data_flag_rx.reset"
|
name="rst_controller.reset_out/data_flag_rx.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="data_flag_rx.reset">
|
end="data_flag_rx.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70751... |
Line 70751... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/data_info.reset"
|
name="rst_controller.reset_out/data_info.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="data_info.reset">
|
end="data_info.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70778... |
Line 70778... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/data_read_en_rx.reset"
|
name="rst_controller.reset_out/data_read_en_rx.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="data_read_en_rx.reset">
|
end="data_read_en_rx.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70805... |
Line 70805... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/fifo_empty_rx_status.reset"
|
name="rst_controller.reset_out/fifo_empty_rx_status.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="fifo_empty_rx_status.reset">
|
end="fifo_empty_rx_status.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70832... |
Line 70832... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/fifo_empty_tx_status.reset"
|
name="rst_controller.reset_out/fifo_empty_tx_status.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="fifo_empty_tx_status.reset">
|
end="fifo_empty_tx_status.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70859... |
Line 70859... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/fifo_full_rx_status.reset"
|
name="rst_controller.reset_out/fifo_full_rx_status.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="fifo_full_rx_status.reset">
|
end="fifo_full_rx_status.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70886... |
Line 70886... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/fifo_full_tx_status.reset"
|
name="rst_controller.reset_out/fifo_full_tx_status.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="fifo_full_tx_status.reset">
|
end="fifo_full_tx_status.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70913... |
Line 70913... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/fsm_info.reset"
|
name="rst_controller.reset_out/fsm_info.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="fsm_info.reset">
|
end="fsm_info.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70940... |
Line 70940... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/led_pio_test.reset"
|
name="rst_controller.reset_out/led_pio_test.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="led_pio_test.reset">
|
end="led_pio_test.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70967... |
Line 70967... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/link_disable.reset"
|
name="rst_controller.reset_out/link_disable.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="link_disable.reset">
|
end="link_disable.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 70994... |
Line 70994... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/link_start.reset"
|
name="rst_controller.reset_out/link_start.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="link_start.reset">
|
end="link_start.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71021... |
Line 71021... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/timecode_ready_rx.reset"
|
name="rst_controller.reset_out/timecode_ready_rx.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="timecode_ready_rx.reset">
|
end="timecode_ready_rx.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71048... |
Line 71048... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/timecode_rx.reset"
|
name="rst_controller.reset_out/timecode_rx.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="timecode_rx.reset">
|
end="timecode_rx.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71075... |
Line 71075... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/timecode_tx_data.reset"
|
name="rst_controller.reset_out/timecode_tx_data.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="timecode_tx_data.reset">
|
end="timecode_tx_data.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71102... |
Line 71102... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/timecode_tx_enable.reset"
|
name="rst_controller.reset_out/timecode_tx_enable.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="timecode_tx_enable.reset">
|
end="timecode_tx_enable.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71129... |
Line 71129... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/timecode_tx_ready.reset"
|
name="rst_controller.reset_out/timecode_tx_ready.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="timecode_tx_ready.reset">
|
end="timecode_tx_ready.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71156... |
Line 71156... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/write_data_fifo_tx.reset"
|
name="rst_controller.reset_out/write_data_fifo_tx.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="write_data_fifo_tx.reset">
|
end="write_data_fifo_tx.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71183... |
Line 71183... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/write_en_tx.reset"
|
name="rst_controller.reset_out/write_en_tx.reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="write_en_tx.reset">
|
end="write_en_tx.reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71210... |
Line 71210... |
reset
|
reset
|
|
|
|
|
name="rst_controller.reset_out/mm_interconnect_0.led_pio_test_reset_reset_bridge_in_reset"
|
name="rst_controller.reset_out/mm_interconnect_0.led_pio_test_reset_reset_bridge_in_reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller.reset_out"
|
start="rst_controller.reset_out"
|
end="mm_interconnect_0.led_pio_test_reset_reset_bridge_in_reset">
|
end="mm_interconnect_0.led_pio_test_reset_reset_bridge_in_reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71237... |
Line 71237... |
led_pio_test_reset_reset_bridge_in_reset
|
led_pio_test_reset_reset_bridge_in_reset
|
|
|
|
|
name="clk_0.clk_reset/rst_controller.reset_in0"
|
name="clk_0.clk_reset/rst_controller.reset_in0"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="rst_controller.reset_in0">
|
end="rst_controller.reset_in0">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71264... |
Line 71264... |
reset_in0
|
reset_in0
|
|
|
|
|
name="clk_0.clk/rst_controller.clk"
|
name="clk_0.clk/rst_controller.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="rst_controller.clk">
|
end="rst_controller.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71291... |
Line 71291... |
clk
|
clk
|
|
|
|
|
name="rst_controller_001.reset_out/mm_interconnect_0.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset"
|
name="rst_controller_001.reset_out/mm_interconnect_0.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="rst_controller_001.reset_out"
|
start="rst_controller_001.reset_out"
|
end="mm_interconnect_0.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset">
|
end="mm_interconnect_0.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71318... |
Line 71318... |
hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset
|
hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset
|
|
|
|
|
name="hps_0_fpga_interfaces.h2f_reset/rst_controller_001.reset_in0"
|
name="hps_0_fpga_interfaces.h2f_reset/rst_controller_001.reset_in0"
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="hps_0_fpga_interfaces.h2f_reset"
|
start="hps_0_fpga_interfaces.h2f_reset"
|
end="rst_controller_001.reset_in0">
|
end="rst_controller_001.reset_in0">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71345... |
Line 71345... |
reset_in0
|
reset_in0
|
|
|
|
|
name="clk_0.clk/rst_controller_001.clk"
|
name="clk_0.clk/rst_controller_001.clk"
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="rst_controller_001.clk">
|
end="rst_controller_001.clk">
|
|
|
java.lang.String
|
java.lang.String
|
UNKNOWN
|
UNKNOWN
|
| Line 71375... |
Line 71375... |
22
|
22
|
altera_avalon_pio
|
altera_avalon_pio
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IModule
|
com.altera.entityinterfaces.IModule
|
PIO (Parallel I/O)
|
PIO (Parallel I/O)
|
17.0
|
17.1
|
|
|
|
|
29
|
29
|
clock_sink
|
clock_sink
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Clock Input
|
Clock Input
|
17.0
|
17.1
|
|
|
|
|
27
|
27
|
reset_sink
|
reset_sink
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Reset Input
|
Reset Input
|
17.0
|
17.1
|
|
|
|
|
22
|
22
|
avalon_slave
|
avalon_slave
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Avalon Memory Mapped Slave
|
Avalon Memory Mapped Slave
|
17.0
|
17.1
|
|
|
|
|
25
|
25
|
conduit_end
|
conduit_end
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Conduit
|
Conduit
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
clock_source
|
clock_source
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IModule
|
com.altera.entityinterfaces.IModule
|
Clock Source
|
Clock Source
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
clock_sink
|
clock_sink
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Clock Input
|
Clock Input
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
reset_sink
|
reset_sink
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Reset Input
|
Reset Input
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
clock_source
|
clock_source
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Clock Output
|
Clock Output
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
reset_source
|
reset_source
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Reset Output
|
Reset Output
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
altera_hps
|
altera_hps
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IModule
|
com.altera.entityinterfaces.IModule
|
Arria V/Cyclone V Hard Processor System
|
Arria V/Cyclone V Hard Processor System
|
17.0
|
17.1
|
|
|
|
|
4
|
4
|
reset_source
|
reset_source
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Reset Output
|
Reset Output
|
17.0
|
17.1
|
|
|
|
|
2
|
2
|
altera_axi_master
|
altera_axi_master
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
AXI Master
|
AXI Master
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
altera_interface_generator
|
altera_interface_generator
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IModule
|
com.altera.entityinterfaces.IModule
|
altera_interface_generator
|
altera_interface_generator
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
altera_hps_io
|
altera_hps_io
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IModule
|
com.altera.entityinterfaces.IModule
|
altera_hps_io
|
altera_hps_io
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
altera_pll
|
altera_pll
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IModule
|
com.altera.entityinterfaces.IModule
|
Altera PLL
|
Altera PLL
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
clock_source
|
clock_source
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Clock Output
|
Clock Output
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
altera_mm_interconnect
|
altera_mm_interconnect
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IModule
|
com.altera.entityinterfaces.IModule
|
MM Interconnect
|
MM Interconnect
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
altera_axi_slave
|
altera_axi_slave
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
AXI Slave
|
AXI Slave
|
17.0
|
17.1
|
|
|
|
|
22
|
22
|
avalon_master
|
avalon_master
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
com.altera.entityinterfaces.IMutableConnectionPoint
|
Avalon Memory Mapped Master
|
Avalon Memory Mapped Master
|
17.0
|
17.1
|
|
|
|
|
2
|
2
|
altera_reset_controller
|
altera_reset_controller
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IModule
|
com.altera.entityinterfaces.IModule
|
Merlin Reset Controller
|
Merlin Reset Controller
|
17.0
|
17.1
|
|
|
|
|
25
|
25
|
clock
|
clock
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IConnection
|
com.altera.entityinterfaces.IConnection
|
Clock Connection
|
Clock Connection
|
17.0
|
17.1
|
|
|
|
|
1
|
1
|
reset
|
reset
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IConnection
|
com.altera.entityinterfaces.IConnection
|
Reset Connection
|
Reset Connection
|
17.0
|
17.1
|
|
|
|
|
23
|
23
|
avalon
|
avalon
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IConnection
|
com.altera.entityinterfaces.IConnection
|
Avalon Memory Mapped Connection
|
Avalon Memory Mapped Connection
|
17.0
|
17.1
|
|
|
|
|
3
|
3
|
clock
|
clock
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IConnection
|
com.altera.entityinterfaces.IConnection
|
Clock Connection
|
Clock Connection
|
17.0
|
17.1
|
|
|
|
|
26
|
26
|
reset
|
reset
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IElementClass
|
com.altera.entityinterfaces.IConnection
|
com.altera.entityinterfaces.IConnection
|
Reset Connection
|
Reset Connection
|
17.0
|
17.1
|
|
|
17.0 598
|
17.1 593
|
5CC9D359BA1A0000015DF058FDC2
|
1C394751E639000001612480705B
|
|
|
