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[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [debounce.v] - Diff between revs 23 and 40

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Rev 23 Rev 40
Line 36... Line 36...
 
 
                    output reg PB_state,
                    output reg PB_state,
                    output reg PB_down
                    output reg PB_down
                  );
                  );
 
 
 
                  reg aux_pb;
                  reg [15:0] counter;
                  reg [15:0] counter;
 
                  //assign PB_state = (counter >= 400)?PB_state:1'b1;
 
always@(*)
 
begin
 
 
 
        PB_state = 1'b1;
 
 
 
        if(CLK)
 
        begin
 
                if(aux_pb)
 
                        PB_state = 1'b0;
 
        end
 
        else if(!CLK)
 
        begin
 
                if(aux_pb)
 
                        PB_state = 1'b0;
 
        end
 
end
 
 
always@(posedge CLK)
always@(posedge CLK)
begin
begin
 
 
        if(PB)
        if(PB)
        begin
        begin
                PB_state<= 1'b1;
                aux_pb  <= 1'b0;
                counter <= 16'd0;
                counter <= 16'd0;
                PB_down <= 1'b0;
                PB_down <= 1'b0;
        end
        end
        else
        else
        begin
        begin
 
 
                if(counter >= 400)
                if(counter >= 400)
                begin
                begin
                        PB_state<= 1'b0;
                        aux_pb  <= 1'b1;
                        PB_down <= 1'b1;
                        PB_down <= 1'b1;
                end
                end
                else
                else
                        counter <= counter + 16'd1;
                        counter <= counter + 16'd1;
 
 

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