| Line 36... |
Line 36... |
parameter integer AWIDTH = 6
|
parameter integer AWIDTH = 6
|
)
|
)
|
|
|
(
|
(
|
input clock, reset, wr_en, rd_en,
|
input clock, reset, wr_en, rd_en,
|
input [DWIDTH-1:0] data_in,
|
input [DWIDTH-1:0] data_in/* synthesis syn_noprune */,
|
output reg f_full,write_tx,f_empty,
|
output reg f_full,write_tx,f_empty,
|
output reg [DWIDTH-1:0] data_out,
|
output [DWIDTH-1:0] data_out/* synthesis syn_noprune */,
|
output reg [AWIDTH-1:0] counter
|
output reg [AWIDTH-1:0] counter/* synthesis syn_noprune */
|
);
|
);
|
|
reg [AWIDTH-1:0] wr_ptr/* synthesis syn_noprune */;
|
reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
|
reg [AWIDTH-1:0] rd_ptr/* synthesis syn_noprune */;
|
|
|
reg [AWIDTH-1:0] wr_ptr;
|
|
reg [AWIDTH-1:0] rd_ptr;
|
|
|
|
reg [1:0] state_data_write;
|
reg [1:0] state_data_write;
|
reg [1:0] next_state_data_write;
|
reg [1:0] next_state_data_write;
|
|
|
reg [1:0] state_data_read;
|
reg [1:0] state_data_read;
|
reg [1:0] next_state_data_read;
|
reg [1:0] next_state_data_read;
|
|
|
|
//reg [AWIDTH-1:0] counter_writer/* synthesis syn_noprune */;
|
|
//reg [AWIDTH-1:0] counter_reader/* synthesis syn_noprune */;
|
|
|
|
|
/****************************************/
|
/****************************************/
|
|
|
always@(*)
|
always@(*)
|
begin
|
begin
|
next_state_data_write = state_data_write;
|
next_state_data_write = state_data_write;
|
| Line 102... |
Line 103... |
next_state_data_read = state_data_read;
|
next_state_data_read = state_data_read;
|
|
|
case(state_data_read)
|
case(state_data_read)
|
2'd0:
|
2'd0:
|
begin
|
begin
|
if(rd_en && !f_empty)
|
if(counter > 6'd0)
|
begin
|
begin
|
next_state_data_read = 2'd1;
|
next_state_data_read = 2'd1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_data_read = 2'd0;
|
next_state_data_read = 2'd0;
|
end
|
end
|
end
|
end
|
2'd1:
|
2'd1:
|
begin
|
begin
|
if(rd_en)
|
if(rd_en && !f_empty)
|
begin
|
begin
|
next_state_data_read = 2'd1;
|
next_state_data_read = 2'd2;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_data_read = 2'd2;
|
next_state_data_read = 2'd1;
|
end
|
end
|
end
|
end
|
2'd2:
|
2'd2:
|
begin
|
begin
|
|
if(rd_en)
|
|
begin
|
|
next_state_data_read = 2'd2;
|
|
end
|
|
else
|
|
begin
|
|
next_state_data_read = 2'd3;
|
|
end
|
|
end
|
|
2'd3:
|
|
begin
|
next_state_data_read = 2'd0;
|
next_state_data_read = 2'd0;
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
next_state_data_read = 2'd0;
|
next_state_data_read = 2'd0;
|
| Line 138... |
Line 150... |
//Write pointer
|
//Write pointer
|
always@(posedge clock or negedge reset)
|
always@(posedge clock or negedge reset)
|
begin
|
begin
|
if (!reset)
|
if (!reset)
|
begin
|
begin
|
mem[0] <= {(DWIDTH){1'b0}};
|
|
mem[1] <= {(DWIDTH){1'b0}};
|
|
mem[2] <= {(DWIDTH){1'b0}};
|
|
mem[3] <= {(DWIDTH){1'b0}};
|
|
mem[4] <= {(DWIDTH){1'b0}};
|
|
mem[5] <= {(DWIDTH){1'b0}};
|
|
mem[6] <= {(DWIDTH){1'b0}};
|
|
mem[7] <= {(DWIDTH){1'b0}};
|
|
mem[8] <= {(DWIDTH){1'b0}};
|
|
mem[9] <= {(DWIDTH){1'b0}};
|
|
mem[10] <= {(DWIDTH){1'b0}};
|
|
|
|
mem[11] <= {(DWIDTH){1'b0}};
|
|
mem[12] <= {(DWIDTH){1'b0}};
|
|
mem[13] <= {(DWIDTH){1'b0}};
|
|
mem[14] <= {(DWIDTH){1'b0}};
|
|
mem[15] <= {(DWIDTH){1'b0}};
|
|
mem[16] <= {(DWIDTH){1'b0}};
|
|
mem[17] <= {(DWIDTH){1'b0}};
|
|
mem[18] <= {(DWIDTH){1'b0}};
|
|
mem[19] <= {(DWIDTH){1'b0}};
|
|
mem[20] <= {(DWIDTH){1'b0}};
|
|
mem[21] <= {(DWIDTH){1'b0}};
|
|
|
|
mem[22] <= {(DWIDTH){1'b0}};
|
|
mem[23] <= {(DWIDTH){1'b0}};
|
|
mem[24] <= {(DWIDTH){1'b0}};
|
|
mem[25] <= {(DWIDTH){1'b0}};
|
|
mem[26] <= {(DWIDTH){1'b0}};
|
|
mem[27] <= {(DWIDTH){1'b0}};
|
|
mem[28] <= {(DWIDTH){1'b0}};
|
|
mem[29] <= {(DWIDTH){1'b0}};
|
|
mem[30] <= {(DWIDTH){1'b0}};
|
|
mem[31] <= {(DWIDTH){1'b0}};
|
|
mem[32] <= {(DWIDTH){1'b0}};
|
|
|
|
|
|
mem[33] <= {(DWIDTH){1'b0}};
|
|
mem[34] <= {(DWIDTH){1'b0}};
|
|
mem[35] <= {(DWIDTH){1'b0}};
|
|
mem[36] <= {(DWIDTH){1'b0}};
|
|
mem[37] <= {(DWIDTH){1'b0}};
|
|
mem[38] <= {(DWIDTH){1'b0}};
|
|
mem[39] <= {(DWIDTH){1'b0}};
|
|
mem[40] <= {(DWIDTH){1'b0}};
|
|
mem[41] <= {(DWIDTH){1'b0}};
|
|
mem[42] <= {(DWIDTH){1'b0}};
|
|
mem[43] <= {(DWIDTH){1'b0}};
|
|
|
|
mem[44] <= {(DWIDTH){1'b0}};
|
|
mem[45] <= {(DWIDTH){1'b0}};
|
|
mem[46] <= {(DWIDTH){1'b0}};
|
|
mem[47] <= {(DWIDTH){1'b0}};
|
|
mem[48] <= {(DWIDTH){1'b0}};
|
|
mem[49] <= {(DWIDTH){1'b0}};
|
|
mem[50] <= {(DWIDTH){1'b0}};
|
|
mem[51] <= {(DWIDTH){1'b0}};
|
|
mem[52] <= {(DWIDTH){1'b0}};
|
|
mem[53] <= {(DWIDTH){1'b0}};
|
|
mem[54] <= {(DWIDTH){1'b0}};
|
|
|
|
mem[55] <= {(DWIDTH){1'b0}};
|
|
mem[56] <= {(DWIDTH){1'b0}};
|
|
mem[57] <= {(DWIDTH){1'b0}};
|
|
mem[58] <= {(DWIDTH){1'b0}};
|
|
mem[59] <= {(DWIDTH){1'b0}};
|
|
mem[60] <= {(DWIDTH){1'b0}};
|
|
mem[61] <= {(DWIDTH){1'b0}};
|
|
mem[62] <= {(DWIDTH){1'b0}};
|
|
mem[63] <= {(DWIDTH){1'b0}};
|
|
|
|
wr_ptr <= {(AWIDTH){1'b0}};
|
wr_ptr <= {(AWIDTH){1'b0}};
|
state_data_write <= 2'd0;
|
state_data_write <= 2'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 220... |
Line 161... |
state_data_write <= next_state_data_write;
|
state_data_write <= next_state_data_write;
|
|
|
case(state_data_write)
|
case(state_data_write)
|
2'd0:
|
2'd0:
|
begin
|
begin
|
mem[wr_ptr]<=mem[wr_ptr];
|
|
wr_ptr <= wr_ptr;
|
wr_ptr <= wr_ptr;
|
end
|
end
|
2'd1:
|
2'd1:
|
begin
|
begin
|
mem[wr_ptr]<=data_in;
|
wr_ptr <= wr_ptr;
|
end
|
end
|
2'd2:
|
2'd2:
|
begin
|
begin
|
wr_ptr <= wr_ptr + 6'd1;
|
wr_ptr <= wr_ptr + 6'd1;
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mem[wr_ptr]<=mem[wr_ptr];
|
|
wr_ptr <= wr_ptr;
|
wr_ptr <= wr_ptr;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
| Line 245... |
Line 184... |
//FULL - EMPTY COUNTER
|
//FULL - EMPTY COUNTER
|
always@(posedge clock or negedge reset)
|
always@(posedge clock or negedge reset)
|
begin
|
begin
|
if (!reset)
|
if (!reset)
|
begin
|
begin
|
|
f_full <= 1'b0;
|
|
f_empty <= 1'b0;
|
counter <= {(AWIDTH){1'b0}};
|
counter <= {(AWIDTH){1'b0}};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
if(state_data_write == 2'd2)
|
if(state_data_write == 2'd2)
|
begin
|
begin
|
if(counter == 6'd63)
|
|
counter <= counter;
|
|
else
|
|
counter <= counter + 6'd1;
|
counter <= counter + 6'd1;
|
end
|
end
|
else if(state_data_read == 2'd2)
|
|
begin
|
|
if(counter == 6'd0)
|
|
counter <= counter;
|
|
else
|
else
|
|
begin
|
|
if(counter > 6'd0 && state_data_read == 2'd3)
|
counter <= counter - 6'd1;
|
counter <= counter - 6'd1;
|
end
|
|
else
|
else
|
begin
|
|
counter <= counter;
|
counter <= counter;
|
end
|
end
|
|
|
end
|
|
end
|
|
|
|
|
|
always@(*)
|
|
begin
|
|
|
|
f_full = 1'b0;
|
|
f_empty = 1'b0;
|
|
|
|
if(counter == 6'd63)
|
if(counter == 6'd63)
|
begin
|
begin
|
f_full = 1'b1;
|
f_full <= 1'b1;
|
|
end
|
|
else
|
|
begin
|
|
f_full <= 1'b0;
|
end
|
end
|
|
|
if(counter == 6'd0)
|
if(counter == 6'd0)
|
begin
|
begin
|
f_empty = 1'b1;
|
f_empty <= 1'b1;
|
|
end
|
|
else
|
|
begin
|
|
f_empty <= 1'b0;
|
|
end
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
//Read pointer
|
//Read pointer
|
always@(posedge clock or negedge reset)
|
always@(posedge clock or negedge reset)
|
begin
|
begin
|
if (!reset)
|
if (!reset)
|
begin
|
begin
|
rd_ptr <= {(AWIDTH){1'b0}};
|
rd_ptr <= {(AWIDTH){1'b0}};
|
data_out <= 9'd0;
|
|
write_tx <= 1'b0;
|
write_tx <= 1'b0;
|
state_data_read <= 2'd0;
|
state_data_read <= 2'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
state_data_read <= next_state_data_read;
|
state_data_read <= next_state_data_read;
|
|
|
case(state_data_read)
|
case(state_data_read)
|
2'd0:
|
2'd0:
|
begin
|
begin
|
if(rd_en)
|
|
begin
|
|
write_tx<= 1'b0;
|
write_tx<= 1'b0;
|
rd_ptr <= rd_ptr + 6'd1;
|
|
end
|
end
|
else
|
2'd1:
|
begin
|
begin
|
data_out <= mem[rd_ptr];
|
if(rd_en && !f_empty)
|
|
|
if(counter > 6'd0)
|
|
begin
|
begin
|
write_tx<= 1'b1;
|
rd_ptr <= rd_ptr + 6'd1;
|
end
|
end
|
else
|
else
|
write_tx<= 1'b0;
|
begin
|
|
rd_ptr <= rd_ptr;
|
end
|
end
|
|
|
|
write_tx<= 1'b1;
|
end
|
end
|
2'd1:
|
2'd2:
|
begin
|
begin
|
write_tx<= 1'b0;
|
write_tx<= 1'b0;
|
data_out <= mem[rd_ptr];
|
|
end
|
end
|
2'd2:
|
2'd3:
|
begin
|
begin
|
write_tx<= 1'b0;
|
write_tx<= 1'b0;
|
data_out <= mem[rd_ptr];
|
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
rd_ptr <= rd_ptr;
|
rd_ptr <= rd_ptr;
|
data_out <= data_out;
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
mem_data mem_dta_fifo_tx(
|
|
|
|
.clock(clock),
|
|
.reset(reset),
|
|
|
|
.data_in(data_in),
|
|
.wr_ptr(wr_ptr),
|
|
.rd_ptr(rd_ptr),
|
|
.data_out(data_out)
|
|
);
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
