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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Diff between revs 34 and 37

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Rev 34	Rev 37
Line 37...	Line 37...
`input rx_din,`	`input rx_din,`
`input rx_sin,`	`input rx_sin,`

`input rx_resetn,`	`input rx_resetn,`

`output reg rx_error,`	`output rx_error,`

`output reg rx_got_bit,`	`output reg rx_got_bit,`
`output reg rx_got_null,`	`output reg rx_got_null,`
`output reg rx_got_nchar,`	`output reg rx_got_nchar,`
`output reg rx_got_time_code,`	`output reg rx_got_time_code,`
Line 61...	Line 61...
`reg data_bit_found;`	`reg data_bit_found;`

`wire posedge_clk;`	`wire posedge_clk;`
`wire negedge_clk;`	`wire negedge_clk;`

	`reg [1:0] state_data_process;`
	`reg [1:0] next_state_data_process;`

`reg bit_c_0;//N`	`reg bit_c_0;//N`
`reg bit_c_1;//P`	`reg bit_c_1;//P`
`reg bit_c_2;//N`	`reg bit_c_2;//N`
`reg bit_c_3;//P`	`reg bit_c_3;//P`

Line 78...	Line 81...
`reg bit_d_7;//P`	`reg bit_d_7;//P`
`reg bit_d_8;//N`	`reg bit_d_8;//N`
`reg bit_d_9;//P`	`reg bit_d_9;//P`

`reg is_control;`	`reg is_control;`
`//reg is_data;`	`reg parity_received;`

`reg last_is_control;`	`reg last_is_control;`
`reg last_is_data;`	`reg last_is_data;`
`reg last_is_timec;`	`reg last_is_timec;`

`reg last_was_control;`	`//reg last_was_control;`
`reg last_was_data;`	`//reg last_was_data;`
`reg last_was_timec;`	`//reg last_was_timec;`

`reg [3:0] control;`	`reg [3:0] control;`
`reg [3:0] control_r;`	`reg [3:0] control_r;`
`reg [3:0] control_p_r;`	`reg [3:0] control_p_r;`
`reg [9:0] data;`	`reg [9:0] data;`
`reg [9:0] timecode;`	`reg [9:0] timecode;`

`reg [3:0] control_l_r;`	`reg [3:0] control_l_r;`
`reg [9:0] data_l_r;`	`//reg [9:0] data_l_r;`

`reg [9:0] dta_timec;`	`reg [9:0] dta_timec;`
`reg [9:0] dta_timec_p;`	`reg [9:0] dta_timec_p;`

`reg rx_data_take;`	`reg rx_data_take;`
`reg rx_data_take_0;`	`reg rx_data_take_0;`

	`reg rx_got_fct_take;`
	`reg rx_got_fct_take_0;`
	`reg rx_got_fct_take_1;`
	`reg rx_got_fct_take_2;`
	`reg rx_got_fct_take_3;`

`reg ready_control;`	`reg ready_control;`
`reg ready_data;`	`reg ready_data;`

`reg ready_control_p;`	`reg ready_control_p;`
`reg ready_data_p;`	`reg ready_data_p;`

`reg ready_control_p_r;`	`reg ready_control_p_r;`
`reg ready_data_p_r;`	`reg ready_data_p_r;`

	`reg parity_rec_c;`
	`reg parity_rec_d;`

	`reg rx_error_c;`
	`reg rx_error_d;`

`reg posedge_p;`	`reg posedge_p;`

`//CLOCK RECOVERY`	`//CLOCK RECOVERY`
`assign posedge_clk = posedge_p;`	`assign posedge_clk = posedge_p;`
`assign negedge_clk = !posedge_p;`	`assign negedge_clk = !posedge_p;`

`assign rx_time_out = timecode[7:0];`	`assign rx_time_out = timecode[7:0];`

	`assign rx_error = rx_error_c \| rx_error_d;`

`always@(*)`	`always@(*)`
`begin`	`begin`

`rx_got_bit = 1'b0;`	`rx_got_bit = 1'b0;`

Line 257...	Line 274...
`begin`	`begin`

`if(!rx_resetn)`	`if(!rx_resetn)`
`begin`	`begin`
`rx_got_fct <= 1'b0;`	`rx_got_fct <= 1'b0;`
	`rx_got_fct_take <= 1'b0;`
	`rx_got_fct_take_0 <= 1'b0;`
	`rx_got_fct_take_1 <= 1'b0;`
	`rx_got_fct_take_2 <= 1'b0;`
	`rx_got_fct_take_3 <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))`	`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))`
`begin`	`begin`
`rx_got_fct <= 1'b1;`	`rx_got_fct_take <= 1'b1;`
	`rx_got_fct_take_0 <= rx_got_fct_take;`
	`rx_got_fct_take_1 <= rx_got_fct_take_0;`
	`rx_got_fct_take_2 <= rx_got_fct_take_1;`
	`rx_got_fct_take_3 <= rx_got_fct_take_2;`
	`rx_got_fct <= rx_got_fct_take \| rx_got_fct_take_0 \| rx_got_fct_take_1 \| rx_got_fct_take_2 \| rx_got_fct_take_3;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`rx_got_fct <= 1'b0;`	`rx_got_fct_take <= 1'b0;`
	`rx_got_fct_take_0 <= rx_got_fct_take;`
	`rx_got_fct_take_1 <= rx_got_fct_take_0;`
	`rx_got_fct_take_2 <= rx_got_fct_take_1;`
	`rx_got_fct_take_3 <= rx_got_fct_take_2;`
	`rx_got_fct <= rx_got_fct_take \| rx_got_fct_take_0 \| rx_got_fct_take_1 \| rx_got_fct_take_2 \| rx_got_fct_take_3;`
`end`	`end`
`end`	`end`
`end`	`end`

`always@(posedge negedge_clk or negedge rx_resetn)`	`always@(posedge negedge_clk or negedge rx_resetn)`
`begin`	`begin`


`if(!rx_resetn)`
`begin`
`rx_error <= 1'b0;`
`end`
`else`
`begin`
`if(last_is_control == 1'b1)`
`begin`
`if(last_was_control == 1'b1)`
`begin`
`if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])`
`begin`
`rx_error <= 1'b1;`
`end`
`else`
`begin`
`rx_error <= 1'b0;`
`end`
`end`
`else if(last_was_timec == 1'b1)`
`begin`
`if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])`
`begin`
`rx_error <= 1'b1;`
`end`
`else`
`begin`
`rx_error <= 1'b0;`
`end`
`end`
`else if(last_was_data == 1'b1)`
`begin`
`if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])`
`begin`
`rx_error <= 1'b1;`
`end`
`else`
`begin`
`rx_error <= 1'b0;`
`end`
`end`

`end`
`else if(last_is_data == 1'b1)`
`begin`
`if(last_was_control == 1'b1)`
`begin`
`if(!(data[8]^control[1]^control[0]) != data[9])`
`begin`
`rx_error <= 1'b1;`
`end`
`else`
`begin`
`rx_error <= 1'b0;`
`end`
`end`
`else if(last_was_timec == 1'b1)`
`begin`
`if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])`
`begin`
`rx_error <= 1'b1;`
`end`
`else`
`begin`
`rx_error <= 1'b0;`
`end`
`end`
`else if(last_was_data == 1'b1)`
`begin`
`if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])`
`begin`
`rx_error <= 1'b1;`
`end`
`else`
`begin`
`rx_error <= 1'b0;`
`end`
`end`
`end`

`end`
`end`

`always@(posedge negedge_clk or negedge rx_resetn)`
`begin`

`if(!rx_resetn)`	`if(!rx_resetn)`
`begin`	`begin`
`rx_got_null <= 1'b0;`	`rx_got_null <= 1'b0;`
`rx_got_nchar <= 1'b0;`	`rx_got_nchar <= 1'b0;`
`rx_got_time_code <= 1'b0;`	`rx_got_time_code <= 1'b0;`
Line 411...	Line 356...

`if(ready_control \|\| ready_control_p)`	`if(ready_control \|\| ready_control_p)`
`begin`	`begin`
`if(is_control)`	`if(is_control)`
`ready_control_p_r <= 1'b1;`	`ready_control_p_r <= 1'b1;`
	`else`
	`ready_control_p_r <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`ready_control_p_r <= 1'b0;`	`ready_control_p_r <= 1'b0;`
`end`	`end`

`if(ready_data \|\| ready_data_p)`	`if(ready_data \|\| ready_data_p)`
`begin`	`begin`
`if(!is_control)`	`if(!is_control)`
`ready_data_p_r <= 1'b1;`	`ready_data_p_r <= 1'b1;`
	`else`
	`ready_data_p_r <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`ready_data_p_r <= 1'b0;`	`ready_data_p_r <= 1'b0;`
`end`	`end`
Line 439...	Line 388...
`always@(posedge ready_control or negedge rx_resetn )`	`always@(posedge ready_control or negedge rx_resetn )`
`begin`	`begin`
`if(!rx_resetn)`	`if(!rx_resetn)`
`begin`	`begin`
`control_r <= 4'd0;`	`control_r <= 4'd0;`
	`parity_rec_c <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`//if(is_control)`
`control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`	`control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`
	`parity_rec_c <= bit_c_3;`
`end`	`end`
`end`	`end`

`always@(posedge ready_control_p or negedge rx_resetn )`	`always@(posedge ready_control_p or negedge rx_resetn )`
`begin`	`begin`
`if(!rx_resetn)`	`if(!rx_resetn)`
`begin`	`begin`
`control_p_r <= 4'd0;`	`control_p_r <= 4'd0;`

`end`	`end`
`else`	`else`
`begin`	`begin`
`//if(is_control)`
`control_p_r <= control_r;`	`control_p_r <= control_r;`
`end`	`end`
`end`	`end`


Line 467...	Line 417...
`always@(posedge ready_data or negedge rx_resetn )`	`always@(posedge ready_data or negedge rx_resetn )`
`begin`	`begin`
`if(!rx_resetn)`	`if(!rx_resetn)`
`begin`	`begin`
`dta_timec <= 10'd0;`	`dta_timec <= 10'd0;`
	`parity_rec_d <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`//if(!is_control)`
`dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`	`dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`
	`parity_rec_d <= bit_d_9;`
`end`	`end`
`end`	`end`


`always@(posedge ready_data_p or negedge rx_resetn )`	`always@(posedge ready_data_p or negedge rx_resetn )`
Line 484...	Line 435...
`begin`	`begin`
`dta_timec_p <= 10'd0;`	`dta_timec_p <= 10'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`//if(!is_control)`
`dta_timec_p <= dta_timec;`	`dta_timec_p <= dta_timec;`
`end`	`end`
`end`	`end`

	`always@(*)`
	`begin`

	`rx_error_d = 1'b0;`

	`if(last_is_control && ready_data_p)`
	`begin`
	`if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)`
	`begin`
	`rx_error_d = 1'b1;`
	`end`
	`end`
	`else if(last_is_data && ready_data_p)`
	`begin`
	`if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)`
	`begin`
	`rx_error_d = 1'b1;`
	`end`
	`end`
	`end`

	`always@(*)`
	`begin`

	`rx_error_c = 1'b0;`

	`if(last_is_control && ready_control_p)`
	`begin`
	`if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)`
	`begin`
	`rx_error_c = 1'b1;`
	`end`
	`end`
	`else if(last_is_data && ready_control_p)`
	`begin`
	`if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)`
	`begin`
	`rx_error_c = 1'b1;`
	`end`
	`end`
	`end`

`always@(posedge negedge_clk or negedge rx_resetn)`	`always@(posedge negedge_clk or negedge rx_resetn)`
`begin`	`begin`

`if(!rx_resetn)`	`if(!rx_resetn)`
`begin`	`begin`
Line 556...	Line 548...
`endcase`	`endcase`

`end`	`end`
`end`	`end`

`always@(posedge posedge_clk or negedge rx_resetn )`	`always@(*)`
`begin`	`begin`

`if(!rx_resetn)`	`next_state_data_process = state_data_process;`

	`case(state_data_process)`
	`2'd0:`
	`begin`
	`if(ready_control_p_r \|\| ready_data_p_r)`
	`begin`
	`next_state_data_process = 2'd1;`
	`end`
	`else`
	`begin`
	`next_state_data_process = 2'd0;`
	`end`
	`end`
	`2'd1:`
	`begin`
	`next_state_data_process = 2'd0;`
	`end`
	`default:`
	`begin`
	`next_state_data_process = 2'd0;`
	`end`
	`endcase`
	`end`


	`always@(posedge negedge_clk or negedge rx_resetn )`
`begin`	`begin`

	`if(!rx_resetn)`
	`begin`
`control_l_r <= 4'd0;`	`control_l_r <= 4'd0;`
`control <= 4'd0;`	`control <= 4'd0;`
`data <= 10'd0;`	`data <= 10'd0;`
`data_l_r <= 10'd0;`	`//data_l_r <= 10'd0;`
`rx_data_flag <= 9'd0;`
`rx_data_take <= 1'b0;`


`timecode <= 10'd0;`
`rx_tick_out <= 1'b0;`

`last_is_control <= 1'b0;`	`last_is_control <= 1'b0;`
`last_is_data <= 1'b0;`	`last_is_data <= 1'b0;`
`last_is_timec <= 1'b0;`	`last_is_timec <= 1'b0;`

`last_was_control <= 1'b0;`	`//last_was_control <= 1'b0;`
`last_was_data <= 1'b0;`	`//last_was_data <= 1'b0;`
`last_was_timec <= 1'b0;`	`//last_was_timec <= 1'b0;`

	`rx_data_flag <= 9'd0;`
	`rx_data_take <= 1'b0;`

	`timecode <= 10'd0;`
	`rx_tick_out <= 1'b0;`

	`state_data_process <= 2'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`

	`state_data_process <= next_state_data_process;`

	`case(state_data_process)`
	`2'd0:`
	`begin`

`if(ready_control_p_r)`	`if(ready_control_p_r)`
`begin`	`begin`
`control <= control_p_r;`	`control <= control_p_r;`
`control_l_r <= control;`	`control_l_r <= control;`

`last_is_control <= 1'b1;`	`last_is_control <= 1'b1;`
`last_is_data <= 1'b0;`	`last_is_data <= 1'b0;`
`last_is_timec <= 1'b0;`	`last_is_timec <= 1'b0;`
`last_was_control <= last_is_control;`	`//last_was_control <= last_is_control;`
`last_was_data <= last_is_data ;`	`//last_was_data <= last_is_data ;`
`last_was_timec <= last_is_timec;`	`//last_was_timec <= last_is_timec;`

	`rx_data_take <= 1'b0;`
	`rx_tick_out <= 1'b0;`

`end`	`end`
`else if(ready_data_p_r)`	`else if(ready_data_p_r)`
`begin`	`begin`

`if(control[2:0] != 3'd7)`	`if(control[2:0] != 3'd7)`
`begin`	`begin`
`rx_data_flag <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};`
`data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};`	`data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};`
`data_l_r <= data;`	`//data_l_r <= data;`
`last_is_control <=1'b0;`	`last_is_control <=1'b0;`
`last_is_data <=1'b1;`	`last_is_data <=1'b1;`
`last_is_timec <=1'b0;`	`last_is_timec <=1'b0;`
`last_was_control <= last_is_control;`	`//last_was_control <= last_is_control;`
`last_was_data <= last_is_data ;`	`//last_was_data <= last_is_data ;`
`last_was_timec <= last_is_timec;`	`//last_was_timec <= last_is_timec;`
`end`	`end`
`else if(control[2:0] == 3'd7)`	`else if(control[2:0] == 3'd7)`
`begin`	`begin`
`timecode <= dta_timec;`
`last_is_control <= 1'b0;`	`last_is_control <= 1'b0;`
`last_is_data <= 1'b0;`	`last_is_data <= 1'b0;`
`last_is_timec <= 1'b1;`	`last_is_timec <= 1'b1;`
`last_was_control <= last_is_control;`	`//last_was_control <= last_is_control;`
`last_was_data <= last_is_data ;`	`//last_was_data <= last_is_data ;`
`last_was_timec <= last_is_timec;`	`//last_was_timec <= last_is_timec;`
`end`	`end`

	`rx_data_take <= 1'b0;`
	`rx_tick_out <= 1'b0;`
`end`	`end`
`else if(last_is_timec == 1'b1)`	`else`
`begin`	`begin`
`rx_data_take <= 1'b0;`	`timecode <= timecode;`
	`end`

	`end`
	`2'd1:`
	`begin`

	`if(last_is_timec == 1'b1)`
	`begin`
	`timecode <= dta_timec;`
`rx_tick_out <= 1'b1;`	`rx_tick_out <= 1'b1;`
`end`	`end`
`else if(last_is_data == 1'b1)`	`else if(last_is_data == 1'b1)`
`begin`	`begin`
	`rx_data_flag <= {data[8],data[7],data[6],data[5],data[4],data[3],data[2],data[1],data[0]};`
`rx_tick_out <= 1'b0;`
`rx_data_take <= 1'b1;`	`rx_data_take <= 1'b1;`
`end`	`end`
`else if(last_is_control == 1'b1)`	`else if(last_is_control == 1'b1)`
`begin`	`begin`

`if(control[2:0] == 3'd6)`	`if(control[2:0] == 3'd6)`
`begin`	`begin`
`rx_data_flag <= 9'd257;`	`rx_data_flag <= 9'd257;`
`rx_data_take <= 1'b1;`	`rx_data_take <= 1'b1;`
`end`	`end`
Line 649...	Line 687...
`rx_data_flag <= 9'd256;`	`rx_data_flag <= 9'd256;`
`rx_data_take <= 1'b1;`	`rx_data_take <= 1'b1;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`rx_data_take <= 1'b0;`	`rx_data_take <= rx_data_take;`
	`rx_tick_out <= rx_tick_out;`
`end`	`end`

`rx_tick_out <= 1'b0;`
`end`	`end`
	`else`
	`begin`

	`rx_data_flag <= rx_data_flag;`
	`rx_data_take <= rx_data_take;`

	`timecode <= timecode;`
	`rx_tick_out <= rx_tick_out;`
	`end`

	`end`
	`default:`
	`begin`
	`rx_data_flag <= rx_data_flag;`
	`rx_data_take <= rx_data_take;`

	`timecode <= timecode;`
	`rx_tick_out <= rx_tick_out;`
	`end`
	`endcase`
`end`	`end`
`end`	`end`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Diff between revs 34 and 37