| Line 87... |
Line 87... |
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reg last_is_control;
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reg last_is_control;
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reg last_is_data;
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reg last_is_data;
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reg last_is_timec;
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reg last_is_timec;
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//reg last_was_control;
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//reg last_was_data;
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//reg last_was_timec;
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reg [3:0] control;
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reg [3:0] control;
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reg [3:0] control_r;
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reg [3:0] control_r;
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reg [3:0] control_p_r;
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reg [3:0] control_p_r;
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reg [9:0] data;
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reg [9:0] data;
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reg [9:0] timecode;
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reg [9:0] timecode;
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reg [3:0] control_l_r;
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reg [3:0] control_l_r;
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//reg [9:0] data_l_r;
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reg [9:0] dta_timec;
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reg [9:0] dta_timec;
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reg [9:0] dta_timec_p;
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reg [9:0] dta_timec_p;
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reg rx_data_take;
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reg rx_data_take_0;
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reg rx_got_fct_take;
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reg rx_got_fct_take_0;
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reg rx_got_fct_take_1;
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reg rx_got_fct_take_2;
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reg rx_got_fct_take_3;
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reg ready_control;
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reg ready_control;
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reg ready_data;
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reg ready_data;
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reg ready_control_p;
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reg ready_control_p;
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reg ready_data_p;
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reg ready_data_p;
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| Line 274... |
Line 260... |
begin
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begin
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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rx_got_fct <= 1'b0;
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rx_got_fct <= 1'b0;
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rx_got_fct_take <= 1'b0;
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rx_got_fct_take_0 <= 1'b0;
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rx_got_fct_take_1 <= 1'b0;
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rx_got_fct_take_2 <= 1'b0;
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rx_got_fct_take_3 <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))
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if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))
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begin
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begin
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rx_got_fct_take <= 1'b1;
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rx_got_fct <= 1'b1;
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rx_got_fct_take_0 <= rx_got_fct_take;
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rx_got_fct_take_1 <= rx_got_fct_take_0;
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rx_got_fct_take_2 <= rx_got_fct_take_1;
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rx_got_fct_take_3 <= rx_got_fct_take_2;
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rx_got_fct <= rx_got_fct_take | rx_got_fct_take_0 | rx_got_fct_take_1 | rx_got_fct_take_2 | rx_got_fct_take_3;
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end
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end
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else
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else
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begin
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begin
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rx_got_fct_take <= 1'b0;
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rx_got_fct <= 1'b0;
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rx_got_fct_take_0 <= rx_got_fct_take;
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rx_got_fct_take_1 <= rx_got_fct_take_0;
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rx_got_fct_take_2 <= rx_got_fct_take_1;
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rx_got_fct_take_3 <= rx_got_fct_take_2;
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rx_got_fct <= rx_got_fct_take | rx_got_fct_take_0 | rx_got_fct_take_1 | rx_got_fct_take_2 | rx_got_fct_take_3;
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end
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end
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end
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end
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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always@(posedge negedge_clk or negedge rx_resetn)
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| Line 340... |
Line 311... |
always@(posedge negedge_clk or negedge rx_resetn)
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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begin
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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rx_got_fct_fsm <= 1'b0;
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rx_got_fct_fsm <= 1'b0;
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rx_buffer_write <= 1'b0;
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rx_data_take_0 <= 1'b0;
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ready_control_p_r <= 1'b0;
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ready_control_p_r <= 1'b0;
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ready_data_p_r <= 1'b0;
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ready_data_p_r <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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rx_data_take_0 <= rx_data_take;
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rx_buffer_write <= rx_data_take_0;
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if(ready_control || ready_control_p)
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if(ready_control || ready_control_p)
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begin
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begin
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if(is_control)
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if(is_control)
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ready_control_p_r <= 1'b1;
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ready_control_p_r <= 1'b1;
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| Line 462... |
Line 428... |
end
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end
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end
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end
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always@(*)
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always@(*)
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begin
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begin
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rx_error_c = 1'b0;
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rx_error_c = 1'b0;
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if(last_is_control && ready_control_p)
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if(last_is_control && ready_control_p)
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begin
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begin
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if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)
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if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)
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| Line 486... |
Line 451... |
always@(posedge negedge_clk or negedge rx_resetn)
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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begin
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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rx_buffer_write <= 1'b0;
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rx_tick_out <= 1'b0;
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end
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else
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begin
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if(!ready_control_p_r && !ready_data_p_r && !ready_control && !ready_data)
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begin
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if(last_is_timec == 1'b1)
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begin
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rx_tick_out <= 1'b1;
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end
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else if(last_is_data == 1'b1)
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begin
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rx_buffer_write <= 1'b1;
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end
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else if(last_is_control == 1'b1)
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begin
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if(control[2:0] == 3'd6)
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begin
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rx_buffer_write <= 1'b1;
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end
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else if(control[2:0] == 3'd5)
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begin
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rx_buffer_write <= 1'b1;
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end
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end
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end
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else
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begin
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rx_buffer_write <= 1'b0;
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rx_tick_out <= 1'b0;
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end
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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if(!rx_resetn)
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begin
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is_control <= 1'b0;
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is_control <= 1'b0;
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control_bit_found <= 1'b0;
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control_bit_found <= 1'b0;
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counter_neg[5:0] <= 6'd1;
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counter_neg[5:0] <= 6'd1;
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end
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end
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else
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else
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| Line 585... |
Line 592... |
if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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control_l_r <= 4'd0;
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control_l_r <= 4'd0;
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control <= 4'd0;
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control <= 4'd0;
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data <= 10'd0;
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data <= 10'd0;
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//data_l_r <= 10'd0;
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last_is_control <= 1'b0;
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last_is_control <= 1'b0;
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last_is_data <= 1'b0;
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last_is_data <= 1'b0;
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last_is_timec <= 1'b0;
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last_is_timec <= 1'b0;
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//last_was_control <= 1'b0;
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//last_was_data <= 1'b0;
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//last_was_timec <= 1'b0;
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rx_data_flag <= 9'd0;
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rx_data_flag <= 9'd0;
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rx_data_take <= 1'b0;
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timecode <= 10'd0;
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timecode <= 10'd0;
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rx_tick_out <= 1'b0;
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state_data_process <= 2'd0;
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state_data_process <= 2'd0;
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end
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end
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else
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else
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begin
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begin
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| Line 617... |
Line 616... |
if(ready_control_p_r)
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if(ready_control_p_r)
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begin
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begin
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control <= control_p_r;
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control <= control_p_r;
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control_l_r <= control;
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control_l_r <= control;
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if(control_p_r[2:0] == 3'd6)
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begin
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rx_data_flag <= 9'd257;
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end
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else if(control_p_r[2:0] == 3'd5)
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begin
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rx_data_flag <= 9'd256;
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end
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else
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begin
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rx_data_flag <= rx_data_flag;
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end
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last_is_control <= 1'b1;
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last_is_control <= 1'b1;
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last_is_data <= 1'b0;
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last_is_data <= 1'b0;
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last_is_timec <= 1'b0;
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last_is_timec <= 1'b0;
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//last_was_control <= last_is_control;
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//last_was_data <= last_is_data ;
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//last_was_timec <= last_is_timec;
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rx_data_take <= 1'b0;
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rx_tick_out <= 1'b0;
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end
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end
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else if(ready_data_p_r)
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else if(ready_data_p_r)
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begin
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begin
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if(control[2:0] != 3'd7)
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if(control[2:0] != 3'd7)
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begin
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begin
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data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
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data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
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//data_l_r <= data;
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rx_data_flag <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
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last_is_control <=1'b0;
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last_is_control <=1'b0;
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last_is_data <=1'b1;
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last_is_data <=1'b1;
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last_is_timec <=1'b0;
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last_is_timec <=1'b0;
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//last_was_control <= last_is_control;
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//last_was_data <= last_is_data ;
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//last_was_timec <= last_is_timec;
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end
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end
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else if(control[2:0] == 3'd7)
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else if(control[2:0] == 3'd7)
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begin
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begin
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timecode <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
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last_is_control <= 1'b0;
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last_is_control <= 1'b0;
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last_is_data <= 1'b0;
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last_is_data <= 1'b0;
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last_is_timec <= 1'b1;
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last_is_timec <= 1'b1;
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//last_was_control <= last_is_control;
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//last_was_data <= last_is_data ;
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//last_was_timec <= last_is_timec;
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end
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end
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rx_data_take <= 1'b0;
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rx_tick_out <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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timecode <= timecode;
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timecode <= timecode;
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end
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end
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end
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end
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2'd1:
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2'd1:
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begin
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begin
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if(last_is_timec == 1'b1)
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begin
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timecode <= dta_timec;
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rx_tick_out <= 1'b1;
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end
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else if(last_is_data == 1'b1)
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begin
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rx_data_flag <= {data[8],data[7],data[6],data[5],data[4],data[3],data[2],data[1],data[0]};
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rx_data_take <= 1'b1;
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end
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else if(last_is_control == 1'b1)
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begin
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if(control[2:0] == 3'd6)
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begin
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rx_data_flag <= 9'd257;
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rx_data_take <= 1'b1;
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end
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else if(control[2:0] == 3'd5)
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begin
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rx_data_flag <= 9'd256;
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rx_data_take <= 1'b1;
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end
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else
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begin
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rx_data_take <= rx_data_take;
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rx_tick_out <= rx_tick_out;
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end
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end
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else
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begin
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rx_data_flag <= rx_data_flag;
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rx_data_flag <= rx_data_flag;
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rx_data_take <= rx_data_take;
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timecode <= timecode;
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timecode <= timecode;
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rx_tick_out <= rx_tick_out;
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end
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end
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end
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default:
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default:
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begin
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begin
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rx_data_flag <= rx_data_flag;
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rx_data_flag <= rx_data_flag;
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rx_data_take <= rx_data_take;
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timecode <= timecode;
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timecode <= timecode;
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rx_tick_out <= rx_tick_out;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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