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https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
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Rev 40 |
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Line 28... |
//Scan Methodology :
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//Scan Methodology :
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//Instantiations :
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//Instantiations :
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//Synthesizable (y/n) :
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//Synthesizable (y/n) :
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//Other :
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//Other :
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//-FHDR------------------------------------------------------------------------
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//-FHDR------------------------------------------------------------------------
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`timescale 1ns/1ns
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module spw_ulight_con_top_x(
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module spw_ulight_con_top_x(
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input ppll_100_MHZ,
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input ppll_100_MHZ,
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input ppllclk,
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input ppllclk,
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input reset_spw_n_b,
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input reset_spw_n_b,
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Line 78... |
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wire [8:0] datarx_flag_axi;
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wire [8:0] datarx_flag_axi;
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wire [8:0] datarx_flag_w;
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wire [8:0] datarx_flag_w;
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wire buffer_write_w;
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wire buffer_write_w;
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wire [7:0] time_out_axi;
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//wire [7:0] time_out_axi;
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wire [13:0] monitor_x_axi;
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//wire [13:0] monitor_x_axi;
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wire [13:0] data_x;
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//wire [13:0] data_x;
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wire rx_buffer_write_mon_x;
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//wire rx_buffer_write_mon_x;
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wire credit_error_rx_w,top_send_fct_now_w;
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wire credit_error_rx_w,top_send_fct_now_w;
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wire top_tx_write_w,top_tx_ready_w;
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wire top_tx_write_w,top_tx_ready_w;
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wire [8:0] top_tx_data_w;
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wire [8:0] top_tx_data_w;
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wire tx_reset_n;
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wire tx_reset_n;
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assign tx_reset_n = (!reset_spw_n_b)?1'b0:1'b1;
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assign tx_reset_n = (!reset_spw_n_b | top_fsm != 6'd16)?1'b0:1'b1;
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//assign time_out = time_out_w;
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//assign time_out = time_out_w;
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assign datarx_flag = datarx_flag_axi;
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assign datarx_flag = datarx_flag_axi;
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//assign data_info = data_x;
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//assign data_info = data_x;
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