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//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME :
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//DEPARTMENT : IC Design / Verification
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH [32,16] : width of the DATA : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy :
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//Clock Domains :
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//Critical Timing :
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//Test Features :
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//Asynchronous I/F :
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//Scan Methodology :
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//Instantiations :
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//Synthesizable (y/n) :
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//Other :
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//-FHDR------------------------------------------------------------------------
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#include <systemc.h>
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#include <systemc.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <vector>
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#include <vector>
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#include <string>
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#include <string>
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#include <stdlib.h>
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#include <stdlib.h>
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Line 12... |
using namespace boost;
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using namespace boost;
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#include "../gladicapi/data_recorder.h"
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#include "../gladicapi/data_recorder.h"
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#include "../gladicapi/data_check.h"
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#include "../gladicapi/data_check.h"
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bool enable_null;
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bool enable_fct;
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bool enable_time_code;
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bool enable_n_char;
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bool EEP_EOP;
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bool EEP_EOP;
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unsigned int finish = 0;
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unsigned int finish = 0;
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bool link_start = false;
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bool link_start = false;
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bool link_disable = false;
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bool link_disable = false;
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| Line 98... |
Line 61... |
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unsigned int data_iteration = 0;
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unsigned int data_iteration = 0;
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unsigned int data_iteration_vlog = 0;
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unsigned int data_iteration_vlog = 0;
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sc_uint<9> intermediate_data;
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sc_uint<9> intermediate_data;
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void data_rx_sc_o(unsigned int type_char, sc_uint<4> control, sc_uint<4> last_control_sys , sc_uint<10> data , sc_uint<10> timecode_sys);
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#include "top_spw.h"
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#include "top_spw.h"
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//Data generation
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//Data generation
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unsigned long int max_data = 100;
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unsigned long int max_data = 255;
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std::random_device rd;
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std::random_device rd;
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std::uniform_int_distribution<unsigned long int> data_in(0,255);
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std::uniform_int_distribution<unsigned long int> data_in(0,255);
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std::uniform_int_distribution<unsigned long int> nchar(1,max_data-1);//eop-eep
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std::uniform_int_distribution<unsigned long int> nchar(1,max_data);//eop-eep
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class sc_TOP_SPW;
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class sc_TOP_SPW;
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SC_MODULE(sc_TOP_SPW)
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SC_MODULE(sc_TOP_SPW)
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{
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{
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| Line 122... |
Line 88... |
sc_signal<sc_uint<4> > FSM_SPW_OUT;
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sc_signal<sc_uint<4> > FSM_SPW_OUT;
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sc_signal<sc_uint<4> > FSM_TX;
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sc_signal<sc_uint<4> > FSM_TX;
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sc_signal<sc_uint<10> > CLOCK_GEN;
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sc_signal<sc_uint<10> > CLOCK_GEN;
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sc_signal<bool> E_SEND_DATA;
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sc_signal<bool> E_SEND_DATA;
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//sc_signal<bool> TICKIN_TX;
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//sc_signal<sc_uint<8> > TIMEIN_CONTROL_FLAG_TX;
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//sc_signal<bool> TXWRITE_TX;
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//sc_signal<sc_uint<9> > TXDATA_FLAGCTRL_TX;
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//sc_signal<bool> READY_TX;
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//sc_signal<bool> READY_TICK;
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sc_signal<bool> BUFFER_READY;
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sc_signal<bool> BUFFER_READY;
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sc_signal<sc_uint<9> > DATARX_FLAG;
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sc_signal<sc_uint<9> > DATARX_FLAG;
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sc_signal<bool> BUFFER_WRITE;
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sc_signal<bool> BUFFER_WRITE;
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| Line 154... |
Line 113... |
LINK_START("LINK_START"),
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LINK_START("LINK_START"),
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AUTO_START("AUTO_START"),
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AUTO_START("AUTO_START"),
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FSM_SPW_OUT("FSM_SPW_OUT"),
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FSM_SPW_OUT("FSM_SPW_OUT"),
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CLOCK_GEN("CLOCK_GEN"),
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CLOCK_GEN("CLOCK_GEN"),
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E_SEND_DATA("E_SEND_DATA"),
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E_SEND_DATA("E_SEND_DATA"),
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//TICKIN_TX("TICKIN_TX"),
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//TIMEIN_CONTROL_FLAG_TX("TIMEIN_CONTROL_FLAG_TX"),
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//TXWRITE_TX("TXWRITE_TX"),
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//TXDATA_FLAGCTRL_TX("TXDATA_FLAGCTRL_TX"),
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//READY_TX("READY_TX"),
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//READY_TICK("READY_TICK"),
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DOUT("DOUT"),
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DOUT("DOUT"),
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SOUT("SOUT"),
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SOUT("SOUT"),
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FSM_TX("FSM_TX"),
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FSM_TX("FSM_TX"),
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DIN("DIN"),
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DIN("DIN"),
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| Line 184... |
Line 136... |
DUT.AUTO_START(AUTO_START);
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DUT.AUTO_START(AUTO_START);
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DUT.LINK_START(LINK_START);
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DUT.LINK_START(LINK_START);
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DUT.FSM_SPW_OUT(FSM_SPW_OUT);
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DUT.FSM_SPW_OUT(FSM_SPW_OUT);
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DUT.CLOCK_GEN(CLOCK_GEN);
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DUT.CLOCK_GEN(CLOCK_GEN);
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DUT.E_SEND_DATA(E_SEND_DATA);
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DUT.E_SEND_DATA(E_SEND_DATA);
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//DUT.TICKIN_TX(TICKIN_TX);
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//DUT.TIMEIN_CONTROL_FLAG_TX(TIMEIN_CONTROL_FLAG_TX);
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//DUT.TXWRITE_TX(TXWRITE_TX);
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//DUT.TXDATA_FLAGCTRL_TX(TXDATA_FLAGCTRL_TX);
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DUT.FSM_TX(FSM_TX);
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DUT.FSM_TX(FSM_TX);
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//DUT.READY_TX(READY_TX);
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//DUT.READY_TICK(READY_TICK);
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DUT.DOUT(DOUT);
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DUT.DOUT(DOUT);
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DUT.SOUT(SOUT);
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DUT.SOUT(SOUT);
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DUT.DIN(DIN);
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DUT.DIN(DIN);
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DUT.SIN(SIN);
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DUT.SIN(SIN);
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| Line 359... |
Line 305... |
else
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else
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{
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{
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enable_time_code_verilog = false;
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enable_time_code_verilog = false;
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}
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}
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/*
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data_generated.clear();
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data_iteration=0;
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data_iteration_vlog=0;
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if(CheckBtnEop->get_active())
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{
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for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
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{
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if(cnt_max_data == 0 || cnt_max_data == max_data)
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{
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intermediate(8,8) = 1;
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intermediate(7,0) = 0;
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}else if(cnt_max_data > 0 && cnt_max_data < max_data)
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{
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intermediate(7,0) = data_in(rd);
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intermediate(8,8) = 0;
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}
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data_generated.push_back(intermediate);
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}
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start_send_data_verilog = true;
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}else if(CheckBtnEep->get_active())
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{
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for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
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{
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if(cnt_max_data == 0 || cnt_max_data == max_data)
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{
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intermediate(8,8) = 1;
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intermediate(7,0) = 1;
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}else if(cnt_max_data > 0 && cnt_max_data < max_data)
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{
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intermediate(7,0) = data_in(rd);
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intermediate(8,8) = 0;
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}
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data_generated.push_back(intermediate);
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}
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intermediate(7,0) = 1;
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intermediate(8,8) = 1;
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data_generated[nchar(rd)] = intermediate;
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start_send_data_verilog = true;
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}
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if(CheckBtnTimeCode->get_active())
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{
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enable_time_code_verilog = true;
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}
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*/
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}
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}
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void on_BtnGenerationDataVerilog_clicked()
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void on_BtnGenerationDataVerilog_clicked()
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{
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{
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data_generated_verilog.clear();
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data_generated_verilog.clear();
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data_iteration=0;
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data_iteration=0;
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data_iteration_vlog=0;
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data_iteration_vlog=0;
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if(CheckBtnEopGenVerilog->get_active())
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if(CheckBtnEopGenVerilog->get_active())
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{
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{
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for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
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for(int cnt_max_data = 0; cnt_max_data < max_data;cnt_max_data++)
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{
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if(cnt_max_data == 0 || cnt_max_data == max_data)
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{
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{
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intermediate_verilog(8,8) = 1;
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if(cnt_max_data >= 0 && cnt_max_data < max_data)
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intermediate_verilog(7,0) = 0;
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}else if(cnt_max_data > 0 && cnt_max_data < max_data)
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{
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{
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intermediate_verilog(7,0) = data_in(rd);
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intermediate_verilog(7,0) = data_in(rd);
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intermediate_verilog(8,8) = 0;
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intermediate_verilog(8,8) = 0;
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}
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data_generated_verilog.push_back(intermediate_verilog);
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data_generated_verilog.push_back(intermediate_verilog);
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}
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}
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intermediate_verilog=0;
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}
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intermediate_verilog(8,8) = 1;
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intermediate_verilog(7,0) = 0;
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data_generated_verilog.push_back(intermediate_verilog);
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intermediate_verilog=0;
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}else if(CheckBtnEepGenVerilog->get_active())
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}else if(CheckBtnEepGenVerilog->get_active())
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{
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{
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for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
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for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
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{
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{
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if(cnt_max_data == 0 || cnt_max_data == max_data)
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if(cnt_max_data == 0 || cnt_max_data == max_data)
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| Line 442... |
Line 345... |
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
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}else if(cnt_max_data > 0 && cnt_max_data < max_data)
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{
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{
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intermediate_verilog(7,0) = data_in(rd);
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intermediate_verilog(7,0) = data_in(rd);
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intermediate_verilog(8,8) = 0;
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intermediate_verilog(8,8) = 0;
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}
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}
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else
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{
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intermediate_verilog(7,0) = data_in(rd);
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intermediate_verilog(8,8) = 0;
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}
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data_generated_verilog.push_back(intermediate_verilog);
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data_generated_verilog.push_back(intermediate_verilog);
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intermediate_verilog=0;
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}
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}
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intermediate_verilog(7,0) = 1;
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intermediate_verilog(7,0) = 1;
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intermediate_verilog(8,8) = 1;
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intermediate_verilog(8,8) = 1;
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data_generated_verilog[nchar(rd)] = intermediate_verilog;
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data_generated_verilog[nchar(rd)] = intermediate_verilog;
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}
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}
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| Line 525... |
Line 434... |
data_generated_sc.clear();
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data_generated_sc.clear();
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data_iteration_sc_aux=0;
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data_iteration_sc_aux=0;
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data_iteration_sc=0;
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data_iteration_sc=0;
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if(CheckBtnEopGenSystemC->get_active())
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if(CheckBtnEopGenSystemC->get_active())
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{
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{
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for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
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for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
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{
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if(cnt_max_data == 0 || cnt_max_data == max_data)
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{
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{
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intermediate_sc(8,8) = 1;
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if(cnt_max_data > 0 && cnt_max_data < max_data)
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intermediate_sc(7,0) = 0;
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}else if(cnt_max_data > 0 && cnt_max_data < max_data)
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{
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{
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intermediate_sc(7,0) = data_in(rd);
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intermediate_sc(7,0) = data_in(rd);
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intermediate_sc(8,8) = 0;
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intermediate_sc(8,8) = 0;
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}
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}
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data_generated_sc.push_back(intermediate_sc);
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data_generated_sc.push_back(intermediate_sc);
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}
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}
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intermediate_sc(8,8) = 1;
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intermediate_sc(7,0) = 0;
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data_generated_sc.push_back(intermediate_verilog);
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intermediate_sc=0;
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}else if(CheckBtnEepGenSystemC->get_active())
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}else if(CheckBtnEepGenSystemC->get_active())
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{
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{
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for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
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for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
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{
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{
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if(cnt_max_data == 0 || cnt_max_data == max_data)
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if(cnt_max_data == 0 || cnt_max_data == max_data)
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| Line 706... |
Line 618... |
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sn_top->E_SEND_DATA = false;
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sn_top->E_SEND_DATA = false;
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sn_top->CLOCK_GEN = 1;
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sn_top->CLOCK_GEN = 1;
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frquency_nano_second = 500;
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frquency_nano_second = 500;
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//sn_top->TICKIN_TX = false;
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//sn_top->TIMEIN_CONTROL_FLAG_TX = 0;
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//sn_top->TXWRITE_TX = false;
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//sn_top->TXDATA_FLAGCTRL_TX = 0;
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}
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}
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void autostart()
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void autostart()
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{
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{
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if(auto_start)
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if(auto_start)
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| Line 868... |
Line 775... |
void Control_SC::end_tx_test()
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void Control_SC::end_tx_test()
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{
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{
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start_send_data_verilog = enable_time_code_verilog = false;
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start_send_data_verilog = enable_time_code_verilog = false;
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}
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}
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int Control_SC::size_data_test()
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int Control_SC::size_data_test_vlog()
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{
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return data_generated_verilog.size();
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}
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int Control_SC::size_data_test_sc()
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{
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{
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return data_generated_verilog.size()-1;
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return data_generated_sc.size();
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}
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}
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unsigned int Control_SC::take_data(unsigned int a)
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unsigned int Control_SC::take_data(unsigned int a)
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{
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{
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intermediate = data_generated_verilog[a];
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intermediate = data_generated_verilog[a];
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| Line 905... |
Line 817... |
{
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{
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data_iteration_sc = 0;
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data_iteration_sc = 0;
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}
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}
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}
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}
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void Control_SC::data_rx_vlog_loopback_o(unsigned int data, unsigned int pos)
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{
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sc_uint<9> intermediate;
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data_col_store.clear();
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data_col_store.push_back("DATA");
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intermediate = data_generated_verilog[pos];
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data_col_store.push_back(intermediate.to_string(SC_HEX));
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intermediate = data;
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data_col_store.push_back(intermediate(8,0).to_string(SC_HEX));
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data_col_store.push_back(" ");
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COMPARE_SPW->compare_test(&data_col_store);
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data_col_store.push_back(sc_time_stamp().to_string());
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REC_TX_SPW->storedata(data_col_store);
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}
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void data_rx_sc_o(unsigned int type_char, sc_uint<4> control, sc_uint<4> last_control_sys , sc_uint<10> data , sc_uint<10> timecode_sys)
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{
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data_col_store.clear();
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switch(type_char)
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{
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case 0:
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data_col_store.push_back("NULL");
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data_col_store.push_back(" - ");
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data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
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data_col_store.push_back(" - ");
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data_col_store.push_back(sc_time_stamp().to_string());
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REC_TX_SPW->storedata(data_col_store);
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break;
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case 1:
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data_col_store.push_back("FCT");
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data_col_store.push_back(" - ");
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data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
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data_col_store.push_back(" - ");
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data_col_store.push_back(sc_time_stamp().to_string());
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REC_TX_SPW->storedata(data_col_store);
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break;
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case 2:
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data_col_store.push_back("EOP");
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intermediate_data = data_generated_verilog[data_iteration];
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data_col_store.push_back(intermediate_data.to_string(SC_HEX));
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data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
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data_col_store.push_back(" ");
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COMPARE_SPW->compare_test(&data_col_store);
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data_iteration++;
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data_col_store.push_back(sc_time_stamp().to_string());
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REC_TX_SPW->storedata(data_col_store);
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break;
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case 3:
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data_col_store.push_back("EEP");
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intermediate_data = data_generated_verilog[data_iteration];
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data_col_store.push_back(intermediate_data.to_string(SC_HEX));
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data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
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data_col_store.push_back(" ");
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COMPARE_SPW->compare_test(&data_col_store);
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data_iteration++;
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data_col_store.push_back(sc_time_stamp().to_string());
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REC_TX_SPW->storedata(data_col_store);
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break;
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case 4:
|
|
data_col_store.push_back("INVALID CONNECTION");
|
|
data_col_store.push_back(" - ");
|
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data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
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data_col_store.push_back(" - ");
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data_col_store.push_back(sc_time_stamp().to_string());
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REC_TX_SPW->storedata(data_col_store);
|
|
break;
|
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case 5:
|
|
data_col_store.push_back("DATA");
|
|
intermediate_data = data_generated_verilog[data_iteration];
|
|
data_col_store.push_back(intermediate_data.to_string(SC_HEX));
|
|
|
|
data_col_store.push_back(data(8,0).to_string(SC_HEX));
|
|
data_col_store.push_back(" ");
|
|
COMPARE_SPW->compare_test(&data_col_store);
|
|
|
|
data_col_store.push_back(sc_time_stamp().to_string());
|
|
REC_TX_SPW->storedata(data_col_store);
|
|
data_iteration++;
|
|
break;
|
|
case 6:
|
|
data_col_store.push_back("TIMECODE");
|
|
data_col_store.push_back(" - ");
|
|
data_col_store.push_back(timecode_sys(7,0).to_string());
|
|
data_col_store.push_back(" - ");
|
|
data_col_store.push_back(sc_time_stamp().to_string());
|
|
REC_TX_SPW->storedata(data_col_store);
|
|
break;
|
|
}
|
|
|
|
}
|
|
|
unsigned int Control_SC::clock_tx()
|
unsigned int Control_SC::clock_tx()
|
{
|
{
|
return sn_top->DUT.CLOCK_TX_OUT.read();
|
return sn_top->DUT.CLOCK_TX_OUT.read();
|
}
|
}
|
|
|
