OpenCores
URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [testbench/] [module_tb.v] - Diff between revs 12 and 40

Show entire file | Details | Blame | View Log

Rev 12 Rev 40
Line 2... Line 2... 
`default_nettype none
 
`default_nettype none
 
 
 
 
 
module module_tb;
 
module module_tb;
 
 
 
 
 
        reg CLK_SIM;
 
        reg CLK_SIM;
 
 
 
        reg CLK_SYS_RX;
 
 
 
 
 
        `ifdef VERILOG_A
 
        `ifdef VERILOG_A
 
 
 
 
 
                /*SPWTCR*/
 
                /*SPWTCR*/
 
                wire CLOCK;
 
                wire CLOCK;
Line 38... Line 39... 
                wire RX_CLOCK_RECOVERY_SC;
 
                wire RX_CLOCK_RECOVERY_SC;
 
                wire TX_CLOCK_RECOVERY_VLOG;
 
                wire TX_CLOCK_RECOVERY_VLOG;
 
                wire TX_CLOCK_OUT;
 
                wire TX_CLOCK_OUT;
 
                wire TX_CLOCK_OUT_SC;
 
                wire TX_CLOCK_OUT_SC;
 
 
 
 
 
 
 
                integer i;
 
 
 
                integer time_clk_ns;
 
 
 
 
 
 
 
                assign SPILL_ENABLE = 1'b1;
 
 
 
 
 
 
 
                initial
 
 
 
                 begin
 
 
 
                        $dumpfile("module_tb.vcd");
 
 
 
                        $dumpvars(0,module_tb);
 
 
 
                        $global_init;
 
 
 
                        i=0;
 
 
 
                        time_clk_ns = 500;
 
 
 
                 end
 
 
 
 
 
                assign RX_CLOCK_RECOVERY_SC = Din ^ Sin;
 
                assign RX_CLOCK_RECOVERY_SC = Din ^ Sin;
 
                assign TX_CLOCK_OUT_SC = TX_CLOCK_OUT;
 
                assign TX_CLOCK_OUT_SC = TX_CLOCK_OUT;
 
                assign SPW_SC_FSM_OUT = SPW_SC_FSM;
 
                assign SPW_SC_FSM_OUT = SPW_SC_FSM;
 
 
 
 
 
                assign TX_CLOCK_RECOVERY_VLOG = Dout ^ Sout;
 
                assign TX_CLOCK_RECOVERY_VLOG = Dout ^ Sout;
Line 49... Line 64... 
                assign CLOCK = CLK;
 
                assign CLOCK = CLK;
 
 
 
 
 
                initial CLK = 1'b0;
 
                initial CLK = 1'b0;
 
                always #(10) CLK = ~CLK;
 
                always #(10) CLK = ~CLK;
 
 
 
 
 
                SpwTCR DUT_TCR (
 
                SPW_TOP DUT_TCR (
 
                                .CLOCK(CLOCK),
 
                                .CLOCK(CLOCK),
 
                                .RESETn(RESETn),
 
                                .RESETn(RESETn),
 
                                .LINK_START(LINK_START),
 
                                .LINK_START(LINK_START),
 
                                .LINK_DISABLE(LINK_DISABLE),
 
                                .LINK_DISABLE(LINK_DISABLE),
 
                                .AUTOSTART(AUTOSTART),
 
                                .AUTOSTART(AUTOSTART),
Line 75... Line 90... 
                                .Sin(Sin),
 
                                .Sin(Sin),
 
                                .Dout(Dout),
 
                                .Dout(Dout),
 
                                .Sout(Sout)
 
                                .Sout(Sout)
 
                        );
 
                        );
 
 
 
 
 
 
 
                        always@(posedge CLK)
 
                        always@(posedge CLK , negedge CLK)
 
 
 
                                $global_reset;
 
                                $global_reset;
 
 
 
 
 
                        always@(posedge CLK)
 
                        always@(posedge CLK)
 
                                $write_tx_spw;
 
                                $write_tx_spw;
 
 
 
 
 
                        always@(posedge CLK)
 
                        always@(posedge CLK)
 
                                $receive_rx_spw;
 
                                $receive_rx_spw;
 
 
 
                        //
 
 
 
                        always@(posedge CLK)
 
 
 
                                $run_sim;
 
 
 
 
 
                        //FLAG USED TO FINISH SIMULATION PROGRAM 
                        //FLAG USED TO FINISH SIMULATION PROGRAM 
                        always@(posedge CLK)
 
                        always@(posedge CLK)
 
                        begin
 
                        begin
 
                                wait(i == 1);
 
                                wait(i == 1);
 
                                $finish();
 
                                $finish();
 
                        end
 
                        end
 
        `endif
 
        `endif
 
 
 
 
 
        `ifdef VERILOG_B
 
        `ifdef VERILOG_B
 
         `endif
 
                assign TOP_SIN = TOP_SOUT;
 
 
 
                assign TOP_DIN = TOP_DOUT;
 
 
 
 
 
 
 
 
 
                integer time_clk_ns;
 
                integer time_clk_ns;
 
 
 
 
 
                reg PCLK;
 
                reg PCLK;
 
 
 
                reg PCLK_FIFO;
 
                reg PPLLCLK;
 
                reg PPLLCLK;
 
 
 
 
 
                wire RESETN;
 
                wire RESETN;
 
 
 
 
 
                wire TOP_SIN;
 
                wire TOP_SIN;
Line 120... Line 140... 
 
 
 
 
                wire CREDIT_ERROR_RX;
 
                wire CREDIT_ERROR_RX;
 
                wire TOP_SEND_FCT_NOW;
 
                wire TOP_SEND_FCT_NOW;
 
 
 
 
 
                wire [8:0] DATARX_FLAG;
 
                wire [8:0] DATARX_FLAG;
 
                wire BUFFER_WRITE;
 
                wire BUFFER_READ;
 
 
 
 
 
                wire [7:0] TIME_OUT;
 
                wire [7:0] TIME_OUT;
 
                wire TICK_OUT;
 
                wire TICK_OUT;
 
 
 
 
 
                wire TOP_DOUT;
 
                wire TOP_DOUT;
Line 132... Line 152... 
 
 
 
 
                wire TOP_TX_READY;
 
                wire TOP_TX_READY;
 
                wire TOP_TX_READY_TICK;
 
                wire TOP_TX_READY_TICK;
 
 
 
 
 
                wire [5:0] TOP_FSM;
 
                wire [5:0] TOP_FSM;
 
 
 
                wire [5:0] COUNTER_FIFO_RX;
 
 
 
                wire [5:0] COUNTER_FIFO_TX;
 
 
 
 
 
                wire TX_CLOCK_RECOVERY_VLOG;
 
                wire TX_CLOCK_RECOVERY_VLOG;
 
                wire [3:0] SPW_SC_FSM;
 
                wire [3:0] SPW_SC_FSM;
 
                wire [3:0] SPW_SC_FSM_OUT;
 
                wire [3:0] SPW_SC_FSM_OUT;
 
 
 
 
 
 
 
                wire [31:0] counter;
 
 
 
                wire [3:0] global_counter_actual;
 
 
 
                wire [13:0] data_took_is;
 
 
 
                wire din_out;
 
 
 
                wire sin_out;
 
 
 
 
 
 
 
                wire F_FULL,F_EMPTY,F_FULL_RX,F_EMPTY_RX;
 
 
 
 
 
                assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT;
 
                assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT;
 
                assign SPW_SC_FSM_OUT = SPW_SC_FSM;
 
                assign SPW_SC_FSM_OUT = SPW_SC_FSM;
 
 
 
 
 
                integer i;
 
                integer i;
 
 
 
 
Line 154... Line 184... 
                 end
 
                 end
 
 
 
 
 
                initial PCLK = 1'b0;
 
                initial PCLK = 1'b0;
 
                always #(5) PCLK = ~PCLK;
 
                always #(5) PCLK = ~PCLK;
 
 
 
 
 
 
 
                initial PCLK_FIFO = 1'b0;
 
 
 
                always #(10) PCLK_FIFO = ~PCLK_FIFO;
 
 
 
 
 
                initial PPLLCLK = 1'b0;
 
                initial PPLLCLK = 1'b0;
 
                always #(time_clk_ns/2) PPLLCLK = ~PPLLCLK;
 
                always #(time_clk_ns/2) PPLLCLK = ~PPLLCLK;
 
 
 
 
 
                initial CLK_SIM = 1'b0;
 
                initial CLK_SIM = 1'b0;
 
                always #(1) CLK_SIM = ~CLK_SIM;
 
                always #(1) CLK_SIM = ~CLK_SIM;
 
 
 
 
 
 
 
                initial CLK_SYS_RX = 1'b0;
 
 
 
                always #(4) CLK_SYS_RX = ~CLK_SYS_RX;
 
 
 
 
 
                top_spw_ultra_light DUT_ULIGHT(
 
                spw_ulight_con_top_x DUT_ULIGHT(
 
                                        .pclk(PCLK),
 
                                        .ppll_100_MHZ(PCLK),
 
                                        .ppllclk(PPLLCLK),
 
                                        .ppllclk(PPLLCLK),
 
                                        .resetn(RESETN),
 
                                        .reset_spw_n_b(RESETN),
 
 
 
 
 
                                        .top_sin(TOP_SIN),
 
                                        .top_sin(TOP_SIN),
 
                                        .top_din(TOP_DIN),
 
                                        .top_din(TOP_DIN),
 
 
 
 
 
                                        .top_auto_start(AUTO_START),
 
                                        .top_auto_start(AUTO_START),
Line 179... Line 214... 
                                        .top_tx_data(TOP_TX_DATA),
 
                                        .top_tx_data(TOP_TX_DATA),
 
 
 
 
 
                                        .top_tx_tick(TOP_TX_TICK),
 
                                        .top_tx_tick(TOP_TX_TICK),
 
                                        .top_tx_time(TOP_TX_TIME),
 
                                        .top_tx_time(TOP_TX_TIME),
 
 
 
 
 
                                        .credit_error_rx(CREDIT_ERROR_RX),
 
 
 
                                        .top_send_fct_now(TOP_SEND_FCT_NOW),
 
 
 
 
 
 
 
                                        .datarx_flag(DATARX_FLAG),
 
                                        .datarx_flag(DATARX_FLAG),
 
                                        .buffer_write(BUFFER_WRITE),
 
                                        .read_rx_fifo_en(BUFFER_READ),
 
 
 
 
 
                                        .time_out(TIME_OUT),
 
                                        .time_out(TIME_OUT),
 
                                        .tick_out(TICK_OUT),
 
                                        .tick_out(TICK_OUT),
 
 
 
 
 
                                        .top_dout(TOP_DOUT),
 
                                        .top_dout(TOP_DOUT),
 
                                        .top_sout(TOP_SOUT),
 
                                        .top_sout(TOP_SOUT),
 
 
 
 
 
                                        .top_tx_ready(TOP_TX_READY),
 
                                        .f_full(F_FULL),
 
 
 
                                        .f_empty(F_EMPTY),
 
 
 
                                        .f_full_rx(F_FULL_RX),
 
 
 
                                        .f_empty_rx(F_EMPTY_RX),
 
                                        .top_tx_ready_tick(TOP_TX_READY_TICK),
 
                                        .top_tx_ready_tick(TOP_TX_READY_TICK),
 
 
 
 
 
                                        .top_fsm(TOP_FSM)
 
                                        .top_fsm(TOP_FSM),
 
 
 
                                        .counter_fifo_tx(COUNTER_FIFO_TX),
 
 
 
                                        .counter_fifo_rx(COUNTER_FIFO_RX)
 
                                      );
 
                                      );
 
 
 
 
 
 
 
 
 
 
 
 
 
        //
 
        //
 
        always@(posedge PCLK)
 
        always@(posedge PCLK_FIFO)
 
                $write_tx_fsm_spw_ultra_light;
 
                $write_tx_fsm_spw_ultra_light;
 
 
 
 
 
        //
 
        //
 
        always@(posedge PCLK or posedge TOP_TX_READY)
 
        always@(posedge PCLK_FIFO)
 
                $write_tx_data_spw_ultra_light;
 
                $write_tx_data_spw_ultra_light;
 
 
 
 
 
        always@(posedge PCLK)
 
        always@(posedge PCLK_FIFO)
 
                $write_tx_time_code_spw_ultra_light;
 
                $write_tx_time_code_spw_ultra_light;
 
 
 
 
 
        //
 
        //
 
        always@(posedge BUFFER_WRITE)
 
        always@(posedge PCLK_FIFO)
 
                $receive_rx_data_spw_ultra_light;
 
                $receive_rx_data_spw_ultra_light;
 
 
 
 
 
        always@(posedge TICK_OUT)
 
        always@(posedge TICK_OUT)
 
                $receive_rx_time_code_spw_ultra_light;
 
                $receive_rx_time_code_spw_ultra_light;
 
 
 
 
Line 230... Line 267... 
        begin
 
        begin
 
                wait(i == 1);
 
                wait(i == 1);
 
                $finish();
 
                $finish();
 
        end
 
        end
 
 
 
 
 
 
 
        `endif
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 No newline at end of file
 
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.