URL https://opencores.org/ocsvn/sparc64soc/sparc64soc/trunk

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[/] [sparc64soc/] [trunk/] [Top/] [W1.v] - Diff between revs 2 and 3

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Rev 2	Rev 3
Line 367...	Line 367...
`);`	`);`

`s1_top cpu (`	`s1_top cpu (`
`.sys_clock_i(wb_clk_i),`	`.sys_clock_i(wb_clk_i),`
`.sys_reset_i(wb_rst_i),`	`.sys_reset_i(wb_rst_i),`
`.sys_irq_i(eth_irq),`	`.eth_irq_i(eth_irq),`
`.wbm_ack_i(m0_ack_o),`	`.wbm_ack_i(m0_ack_o),`
`.wbm_data_i(m0_dat_o),`	`.wbm_data_i(m0_dat_o),`
`.wbm_cycle_o(m0_cyc_i),`	`.wbm_cycle_o(m0_cyc_i),`
`.wbm_strobe_o(m0_stb_i),`	`.wbm_strobe_o(m0_stb_i),`
`.wbm_we_o(m0_we_i),`	`.wbm_we_o(m0_we_i),`
`.wbm_addr_o(m0_adr_i),`	`.wbm_addr_o(m0_adr_i),`
`.wbm_data_o(m0_dat_i),`	`.wbm_data_o(m0_dat_i),`
`.wbm_sel_o(m0_sel_i)`	`.wbm_sel_o(m0_sel_i)`
`);`	`);`

	`wire [7:0] fifo_used;`

`dram_wb dram_wb_inst (`	`dram_wb dram_wb_inst (`
`.clk200(sysclk),`	`.clk200(sysclk),`
`.rup(rup),`	`.rup(rup),`
`.rdn(rdn),`	`.rdn(rdn),`
`.wb_clk_i(wb_clk_i),`	`.wb_clk_i(wb_clk_i),`
Line 412...	Line 414...
`.ddr3_odt(ddr3_odt),`	`.ddr3_odt(ddr3_odt),`
`.ddr3_ce(ddr3_ce),`	`.ddr3_ce(ddr3_ce),`
`.ddr3_dm(ddr3_dm),`	`.ddr3_dm(ddr3_dm),`
`.phy_init_done(phy_init_done),`	`.phy_init_done(phy_init_done),`
`.dcm_locked(dcm_locked),`	`.dcm_locked(dcm_locked),`
	`.fifo_used(fifo_used),`
`.sysrst(sysrst)`	`.sysrst(sysrst)`
`);`	`);`

`WBFLASH flash (`	`WBFLASH flash (`
`.wb_clk_i(wb_clk_i),`	`.wb_clk_i(wb_clk_i),`
Line 512...	Line 515...
`.led_link(led_link),`	`.led_link(led_link),`

`.md(md),`	`.md(md),`
`.mdc(mdc),`	`.mdc(mdc),`

`int_eth(eth_int)`	`.int_eth(eth_int)`
`);`	`);`

`assign eth_rst=!wb_rst_i; // PHY reset`	`assign eth_rst=!wb_rst_i; // PHY reset`

`wire sysrst_p;`	`wire sysrst_p;`
Line 615...	Line 618...
`end`	`end`
`endcase`	`endcase`
`ILA_DATA[204]<=stx;`	`ILA_DATA[204]<=stx;`
`ILA_DATA[205]<=srx;`	`ILA_DATA[205]<=srx;`
`ILA_DATA[206]<=baud_o;`	`ILA_DATA[206]<=baud_o;`
`ILA_DATA[220:207]<=cycle_count[31:18];`	`//ILA_DATA[220:207]<=cycle_count[31:18];`
	`ILA_DATA[220:213]<=fifo_used;`
	`ILA_DATA[212:207]<=cycle_count[31:26];`
`ILA_DATA[221]<=dcm_locked;`	`ILA_DATA[221]<=dcm_locked;`
`ILA_DATA[222]<=wb_rst_i;`	`ILA_DATA[222]<=wb_rst_i;`
`ILA_DATA[223]<=phy_init_done;`	`ILA_DATA[223]<=phy_init_done;`
`end`	`end`

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[/] [sparc64soc/] [trunk/] [Top/] [W1.v] - Diff between revs 2 and 3