ࡱ > [ | bjbj {b ΐ ΐ b! b! . . / / / $ $/ $/ $/ P t/ D / $/ G 0 :1 ^ 1 1 1 2 q4 | 4 @ F F F F F F F H K F / -5 2 2 -5 -5 F . . 1 1 ; F 9 9 9 -5 B . 8 1 / 1 F 9 -5 F 9 9 2 C . E 1
5b $/ o6 wE . F F 0 G E . L 7 L \ E L / E -5 -5 9 -5 -5 -5 -5 -5 F F !8 -5 -5 -5 G -5 -5 -5 -5 L -5 -5 -5 -5 -5 -5 -5 -5 -5 b! v- : HYPERLINK "http://www.opencores.org"
SPI Master / Slave CoreSpecification
SPI_MASTER_SLAVE
SPI Master and Slave Interfaces
VHDL
RTL Architecture
Author: Jonny Doin
jdoin@opencores.org
Rev. 0.95
TIME \@ "MMMM d, yyyy" May 29, 2011
Revision History
Rev.DateAuthorDescription 0.111/05/18JDFirst Draft
Described the SPI_MASTER and SPI_SLAVE cores.
Contents
TOC \t "Heading 3,2,Index,1,Appendix A,1,Heading 2 name,1,Appendix B,1" Introduction 1
Architecture 2
Operation PAGEREF _Toc518887502 \h 3
Clocks 5
IO Ports 6
Appendix A PAGEREF _Toc518887508 \h 7
Appendix B PAGEREF _Toc518887509 \h 8
Index PAGEREF _Toc518887510 \h 9
Introduction
The SPI_MASTER_SLAVE core implements two related but independent design blocks: the SPI_MASTER and the SPI_SLAVE blocks.
Each core is a small RTL description for the widely used Serial Peripheral Interface, written in VHDL.
The SPI bus signals follow the de-facto standard for the SPI interface, and are named after the Motorola original naming convention, with the 4 SPI signals (SSEL, SCK, MOSI, MISO). The SPI mode and serial word size can be controlled at instantiation by VHDL generics.
There are two interfaces to each core, the SPI bus interface, with the SPI signals, and the parallel read/write interface. The cores work on 2 asynchronous clock domains, the SPI bus clock, SCK, and the user internal logic clock, to which the parallel interfaces are synchronous.
All operation is fully static, and the parallel interface is simple to use, similar to a synchronous RAM block.
Architecture
Each core is implemented as a single design entity. The block diagram for each core is detailed below:
Each core has 2 interfaces, the SPI bus and the parallel data I/O ports. Separate clock domains inside the cores synchronize the operations of the core RTL registers and the parallel I/O ports.
The spi_master core generates the spi_sck_o clock by dividing input clock spi_2x_clk_i.
Small but significant differences exist in the state machines of the master and slave functions to have specialized cores for each function. Instead of making a universal master/slave core with runtime selection of operation mode, the function and mode are selected during instantiation, using generics, to achieve efficient silicon usage.
Operation
The internal logic of each core is a sequencer implemented as a single RTL state machine. The state machine is clocked by the SPI SCK clock. The spi_master block generates the spi clock from a 2x input clock, using 2 FFDs to derive two in-phase clocks, one continuous clock to control the sequencer, and an output spi clock, that is controlled with the CE input of a second FFD. Both clocks have high phase correlation, so serial data change is synchronous to the output SCK generated.
The SPI bus has 4 modes of operation, controlled by 2 parameters: Clock Polarity (CPOL) and Clock Phase (CPHA). The master and slave in a SPI connection must have the same SPI mode to interoperate. The modes are depicted in the following waveform diagram.
Serial data output signal changes at the clock edge selected by CPOL and CPHA.
The serial data input is sampled at the opposite clock edge. Data setup time to the data sampling edge is the limiting factor for maximum SPI operating frequency. If transmit-only operation is intended, the master can achieve a much higher clock frequency.
The model has generics to control generation of SPI mode, word width and data prefetch timing.
The operation of the spi_master block starts with a write to the parallel data in port.
Clocks
[This section specifies all the clocks. All clocks, clock domain passes and the clock relations should be described.]
NameSourceRates (MHz)RemarksDescriptionMaxMinResolutionclk_pad_iInput Pad1040.1Duty cycle 70/30.For external interface.wb_clk_IPLL200--Must be synchronized to sm_clk_iSystem clock.sm_clk_iInput port55401There are multi-clocks paths.Clock 55MHz for State machine.Table SEQ Table \* ARABIC 1: List of clocks
IO Ports
[This section specifies the core IO ports.]
PortWidthDirectionDescriptionwb_clk_i1InputBlocks WISHBONE Clock Inputwb_rst_i1InputBlocks WISHBONE Reset Inputwb_sel_i4InputBlocks WISHBONE Select Inputsfoo_pad_o1OutputBlocks foo output to output padTable SEQ Table \* ARABIC 2: List of IO ports
Name
[This section may be added to outline different specifications.]
Name
[This section may be added to outline different specifications.]
[This section contains an alphabetical list of helpful document entries with their corresponding page numbers.]
SPI_MASTER_SLAVE
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.95 Preliminary PAGE ii
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.95 - Preliminary PAGE 9 of SECTIONPAGES9
' ( ) * + , . @ T U V g Ʒyryrkd]dQdQ j h9 5CJ U
hm} 5CJ
h9 5CJ
hh 5CJ
hQ 6CJ
h9 6CJ
h9 5CJ4 #hh hh 5OJ QJ ^J nHtH+hh hh 5CJ$ OJ QJ ^J aJ$ nHtHhh nHtH h{> hh CJH aJH nHtH h{> h9 CJH aJH h{> h{> CJH aJH h9 j hK Uj h UhK j hK U , - . T U V g " $If $ a$ $
f!a$gd{> $a$ $
f!a$ @^@gdh gdh ( ) * / 1 2 4 5 7 8 : ; F G u y z ~
|
ࡱ > g ,6 bjbjVV { r< r< ,- b! b! . . . . . $ . . . P ;/ d / . JS | 0 91 ^ 1 1 1 r2 4 | 4 @ R R R R R R R $ U xX . R . 4 r2 r2 4 4 R . . 1 1 S <= <= <= 4 . 1 . 1 R <= 4 R <= <= N Q 1 z* : P 4 R S 0 JS P Y l; $ Y h Q Y . Q $ 4 4 <= 4 4 4 4 4 R R <
|