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[/] [spi_master_slave/] [trunk/] [syn/] [grp_debouncer.vhd] - Diff between revs 10 and 12

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-- Author:          Jonny Doin, jdoin@opencores.org
-- Author:          Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
-- 
-- 
-- Create Date:     09:56:30 07/06/2011  
-- Create Date:     09:56:30 07/06/2011  
-- Module Name:     grp_debouncer - RTL
-- Module Name:     grp_debouncer - RTL
-- Project Name:    basic functions
-- Project Name:    basic functions
-- Target Devices:  Spartan-6
-- Target Devices:  Spartan-6
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--      The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers.
--      The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers.
--      The number of LUTs inferred is roughly: ((4*N+2)/6)+2.
--      The number of LUTs inferred is roughly: ((4*N+2)/6)+2.
--      The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r.
--      The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r.
--
--
--      This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
--      This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
 
--      Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i.
--      The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
--      The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
--
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--                                                                   
--                                                                   
--                                                                   
--                                                                   
--      Author(s):      Jonny Doin, jdoin@opencores.org
--      Author(s):      Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
--                                                                   
--                                                                   
--      Copyright (C) 2011 Authors
--      Copyright (C) 2011 Authors
--      --------------------------
--      --------------------------
--                                                                   
--                                                                   
--      This source file may be used and distributed without restriction provided that this copyright statement is not    
--      This source file may be used and distributed without restriction provided that this copyright statement is not    
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--
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--  TODO
--  TODO
--  ====
--  ====
--
--
 
--  The circuit can easily be extended to have a signature of which inputs changed at the data out port.
--
--
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library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
 
 

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