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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master.vhd] - Diff between revs 16 and 22

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-- There are several output ports that are used to simulate and verify the core operation. 
-- There are several output ports that are used to simulate and verify the core operation. 
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry. 
-- circuitry. 
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- synthesis tool will remove the receive logic from the generated circuitry.
 
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
 
-- integrated to your circuit.
--================================================================================================================
--================================================================================================================
 
 
entity spi_master is
entity spi_master is
    Generic (
    Generic (
        N : positive := 32;                                             -- 32bit serial word length is default
        N : positive := 32;                                             -- 32bit serial word length is default
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--================================================================================================================
--================================================================================================================
-- this architecture is a pipelined register-transfer description.
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
--================================================================================================================
architecture rtl of spi_master is
architecture rtl of spi_master is
    -- core clocks, generated from 'sclk_i': initialized to differential values
    -- core clocks, generated from 'sclk_i': initialized at GSR to differential values
    signal core_clk     : std_logic := '0';     -- continuous core clock, positive logic
    signal core_clk     : std_logic := '0';     -- continuous core clock, positive logic
    signal core_n_clk   : std_logic := '1';     -- continuous core clock, negative logic
    signal core_n_clk   : std_logic := '1';     -- continuous core clock, negative logic
    signal core_ce      : std_logic := '0';     -- core clock enable, positive logic
    signal core_ce      : std_logic := '0';     -- core clock enable, positive logic
    signal core_n_ce    : std_logic := '1';     -- core clock enable, negative logic
    signal core_n_ce    : std_logic := '1';     -- core clock enable, negative logic
    -- spi bus clock, generated from the CPOL selected core clock polarity
    -- spi bus clock, generated from the CPOL selected core clock polarity
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    --  CLOCK GENERATION
    --  CLOCK GENERATION
    --=============================================================================================
    --=============================================================================================
    -- In order to preserve global clocking resources, the core clocking scheme is completely based 
    -- In order to preserve global clocking resources, the core clocking scheme is completely based 
    -- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
    -- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
    -- the spi clock generator and the input sampling clock.
    -- the spi clock generator and the input sampling clock.
    -- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock 
    -- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock 
    -- for the core clocking.
    -- for the core clocking.
    -- The 2 clock phases are generated by separate and synchronous FFs, and should have only 
    -- The 2 clock phases are generated by separate and synchronous FFs, and should have only 
    -- differential interconnect delay skew.
    -- differential interconnect delay skew.
    -- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock 
    -- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock 
    -- enables are used to control clocking of all internal synchronous circuitry. 
    -- enables are used to control clocking of all internal synchronous circuitry. 

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