| Line 1... |
Line 1... |
Release 13.1 - xst O.40d (nt)
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Release 13.1 - xst O.40d (nt)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
|
--> Parameter TMPDIR set to xst/projnav.tmp
|
--> Parameter TMPDIR set to xst/projnav.tmp
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|
|
|
|
Total REAL time to Xst completion: 1.00 secs
|
Total REAL time to Xst completion: 0.00 secs
|
Total CPU time to Xst completion: 0.09 secs
|
Total CPU time to Xst completion: 0.08 secs
|
|
|
--> Parameter xsthdpdir set to xst
|
--> Parameter xsthdpdir set to xst
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|
|
|
|
Total REAL time to Xst completion: 1.00 secs
|
Total REAL time to Xst completion: 0.00 secs
|
Total CPU time to Xst completion: 0.09 secs
|
Total CPU time to Xst completion: 0.08 secs
|
|
|
--> Reading design: spi_master_atlys_top.prj
|
--> Reading design: spi_master_atlys_top.prj
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TABLE OF CONTENTS
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TABLE OF CONTENTS
|
1) Synthesis Options Summary
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1) Synthesis Options Summary
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| Line 102... |
Line 102... |
|
|
|
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=========================================================================
|
=========================================================================
|
* HDL Parsing *
|
* HDL Parsing *
|
=========================================================================
|
=========================================================================
|
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work
|
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work
|
Parsing entity .
|
Parsing entity .
|
Parsing architecture of entity .
|
Parsing architecture of entity .
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 347: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 361: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 355: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 369: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 364: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 378: Case choice must be a locally static expression
|
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" into library work
|
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" into library work
|
Parsing entity .
|
Parsing entity .
|
Parsing architecture of entity .
|
Parsing architecture of entity .
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 503: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 505: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 511: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 513: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 519: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 521: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 528: Case choice must be a locally static expression
|
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 530: Case choice must be a locally static expression
|
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work
|
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work
|
Parsing entity .
|
Parsing entity .
|
Parsing architecture of entity .
|
Parsing architecture of entity .
|
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work
|
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work
|
Parsing entity .
|
Parsing entity .
|
Parsing architecture of entity .
|
Parsing architecture of entity .
|
|
|
=========================================================================
|
=========================================================================
|
* HDL Elaboration *
|
* HDL Elaboration *
|
=========================================================================
|
=========================================================================
|
|
|
Elaborating entity (architecture ) from library .
|
Elaborating entity (architecture ) with generics from library .
|
|
|
Elaborating entity (architecture ) with generics from library .
|
Elaborating entity (architecture ) with generics from library .
|
|
|
Elaborating entity (architecture ) with generics from library .
|
Elaborating entity (architecture ) with generics from library .
|
|
|
Elaborating entity (architecture ) with generics from library .
|
Elaborating entity (architecture ) with generics from library .
|
|
|
Elaborating entity (architecture ) with generics from library .
|
Elaborating entity (architecture ) with generics from library .
|
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 456. Case statement is complete. others clause is never selected
|
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 459. Case statement is complete. others clause is never selected
|
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 517. Case statement is complete. others clause is never selected
|
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 521. Case statement is complete. others clause is never selected
|
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 567. Case statement is complete. others clause is never selected
|
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 571. Case statement is complete. others clause is never selected
|
WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 174: Net does not have a driver.
|
|
|
|
=========================================================================
|
=========================================================================
|
* HDL Synthesis *
|
* HDL Synthesis *
|
=========================================================================
|
=========================================================================
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".
|
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port of the instance is unconnected or connected to loadless signal.
|
N = 8
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port of the instance is unconnected or connected to loadless signal.
|
CPOL = '0'
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port of the instance is unconnected or connected to loadless signal.
|
CPHA = '0'
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port of the instance is unconnected or connected to loadless signal.
|
PREFETCH = 3
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 221: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 230: Output port of the instance is unconnected or connected to loadless signal.
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port of the instance is unconnected or connected to loadless signal.
|
WARNING:Xst:2935 - Signal 'dbg<3:0>', unconnected in block 'spi_master_atlys_top', is tied to its initial value (0000).
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port of the instance is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port of the instance is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 224: Output port of the instance is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 233: Output port of the instance is unconnected or connected to loadless signal.
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 8-bit register for signal .
|
Found 8-bit register for signal .
|
| Line 226... |
Line 228... |
| Reset State | st_reset |
|
| Reset State | st_reset |
|
| Power Up State | st_reset |
|
| Power Up State | st_reset |
|
| Encoding | Gray |
|
| Encoding | Gray |
|
| Implementation | LUT |
|
| Implementation | LUT |
|
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
Found 1-bit adder for signal > created at line 273.
|
Found 1-bit adder for signal > created at line 276.
|
Found 1-bit adder for signal > created at line 287.
|
Found 1-bit adder for signal > created at line 290.
|
Found 8-bit comparator equal for signal <_n0380> created at line 359
|
Found 8-bit comparator equal for signal <_n0380> created at line 362
|
Found 6-bit comparator equal for signal <_n0400> created at line 362
|
Found 6-bit comparator equal for signal <_n0400> created at line 365
|
Summary:
|
Summary:
|
inferred 2 Adder/Subtractor(s).
|
inferred 2 Adder/Subtractor(s).
|
inferred 71 D-type flip-flop(s).
|
inferred 71 D-type flip-flop(s).
|
inferred 2 Comparator(s).
|
inferred 2 Comparator(s).
|
inferred 5 Multiplexer(s).
|
inferred 5 Multiplexer(s).
|
inferred 3 Finite State Machine(s).
|
inferred 3 Finite State Machine(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master.vhd".
|
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master.vhd".
|
N = 8
|
N = 8
|
CPOL = '0'
|
CPOL = '0'
|
CPHA = '0'
|
CPHA = '0'
|
PREFETCH = 3
|
PREFETCH = 3
|
SPI_2X_CLK_DIV = 1
|
SPI_2X_CLK_DIV = 1
|
| Line 273... |
Line 275... |
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit adder for signal > created at line 328.
|
Found 1-bit adder for signal > created at line 330.
|
Found 4-bit subtractor for signal > created at line 526.
|
Found 4-bit subtractor for signal > created at line 528.
|
Found 4-bit comparator greater for signal created at line 519
|
Found 4-bit comparator greater for signal created at line 521
|
Found 4-bit comparator greater for signal created at line 519
|
Found 4-bit comparator greater for signal created at line 521
|
Found 4-bit comparator greater for signal created at line 528
|
Found 4-bit comparator greater for signal created at line 530
|
Found 4-bit comparator greater for signal created at line 528
|
Found 4-bit comparator greater for signal created at line 530
|
Summary:
|
Summary:
|
inferred 2 Adder/Subtractor(s).
|
inferred 2 Adder/Subtractor(s).
|
inferred 52 D-type flip-flop(s).
|
inferred 52 D-type flip-flop(s).
|
inferred 4 Comparator(s).
|
inferred 4 Comparator(s).
|
inferred 13 Multiplexer(s).
|
inferred 13 Multiplexer(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_slave.vhd".
|
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_slave.vhd".
|
N = 8
|
N = 8
|
CPOL = '0'
|
CPOL = '0'
|
CPHA = '0'
|
CPHA = '0'
|
PREFETCH = 3
|
PREFETCH = 3
|
|
Found 1-bit register for signal .
|
Found 4-bit register for signal .
|
Found 4-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
| Line 311... |
Line 314... |
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 4-bit subtractor for signal > created at line 362.
|
Found 4-bit subtractor for signal > created at line 376.
|
Found 4-bit comparator greater for signal created at line 355
|
Found 4-bit comparator greater for signal created at line 369
|
Found 4-bit comparator greater for signal created at line 355
|
Found 4-bit comparator greater for signal created at line 369
|
Found 4-bit comparator greater for signal created at line 364
|
Found 4-bit comparator greater for signal created at line 378
|
Found 4-bit comparator greater for signal created at line 364
|
Found 4-bit comparator greater for signal created at line 378
|
Summary:
|
Summary:
|
inferred 1 Adder/Subtractor(s).
|
inferred 1 Adder/Subtractor(s).
|
inferred 43 D-type flip-flop(s).
|
inferred 44 D-type flip-flop(s).
|
inferred 4 Comparator(s).
|
inferred 4 Comparator(s).
|
inferred 22 Multiplexer(s).
|
inferred 22 Multiplexer(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
|
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
|
N = 8
|
N = 8
|
CNT_VAL = 200
|
CNT_VAL = 20000
|
Found 8-bit register for signal .
|
Found 8-bit register for signal .
|
Found 8-bit register for signal .
|
Found 8-bit register for signal .
|
Found 8-bit register for signal .
|
Found 8-bit register for signal .
|
Found 8-bit register for signal .
|
Found 15-bit register for signal .
|
Found 9-bit adder for signal created at line 162.
|
Found 16-bit adder for signal created at line 162.
|
Found 8-bit comparator not equal for signal created at line 184
|
Found 8-bit comparator not equal for signal created at line 184
|
Found 8-bit comparator not equal for signal created at line 190
|
Found 8-bit comparator not equal for signal created at line 190
|
Summary:
|
Summary:
|
inferred 1 Adder/Subtractor(s).
|
inferred 1 Adder/Subtractor(s).
|
inferred 32 D-type flip-flop(s).
|
inferred 39 D-type flip-flop(s).
|
inferred 2 Comparator(s).
|
inferred 2 Comparator(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
|
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
|
N = 6
|
N = 6
|
CNT_VAL = 200
|
CNT_VAL = 20000
|
Found 6-bit register for signal .
|
Found 6-bit register for signal .
|
Found 6-bit register for signal .
|
Found 6-bit register for signal .
|
Found 6-bit register for signal .
|
Found 6-bit register for signal .
|
Found 8-bit register for signal .
|
Found 15-bit register for signal .
|
Found 9-bit adder for signal created at line 162.
|
Found 16-bit adder for signal created at line 162.
|
Found 6-bit comparator not equal for signal created at line 184
|
Found 6-bit comparator not equal for signal created at line 184
|
Found 6-bit comparator not equal for signal created at line 190
|
Found 6-bit comparator not equal for signal created at line 190
|
Summary:
|
Summary:
|
inferred 1 Adder/Subtractor(s).
|
inferred 1 Adder/Subtractor(s).
|
inferred 26 D-type flip-flop(s).
|
inferred 33 D-type flip-flop(s).
|
inferred 2 Comparator(s).
|
inferred 2 Comparator(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
=========================================================================
|
=========================================================================
|
HDL Synthesis Report
|
HDL Synthesis Report
|
|
|
Macro Statistics
|
Macro Statistics
|
# Adders/Subtractors : 7
|
# Adders/Subtractors : 7
|
1-bit adder : 3
|
1-bit adder : 3
|
|
16-bit adder : 2
|
4-bit subtractor : 2
|
4-bit subtractor : 2
|
9-bit adder : 2
|
# Registers : 73
|
# Registers : 72
|
1-bit register : 49
|
1-bit register : 48
|
15-bit register : 2
|
4-bit register : 2
|
4-bit register : 2
|
6-bit register : 4
|
6-bit register : 4
|
8-bit register : 18
|
8-bit register : 16
|
# Comparators : 14
|
# Comparators : 14
|
4-bit comparator greater : 8
|
4-bit comparator greater : 8
|
6-bit comparator equal : 1
|
6-bit comparator equal : 1
|
6-bit comparator not equal : 2
|
6-bit comparator not equal : 2
|
8-bit comparator equal : 1
|
8-bit comparator equal : 1
|
| Line 420... |
Line 424... |
Macro Statistics
|
Macro Statistics
|
# Adders/Subtractors : 2
|
# Adders/Subtractors : 2
|
4-bit subtractor : 2
|
4-bit subtractor : 2
|
# Counters : 5
|
# Counters : 5
|
1-bit up counter : 3
|
1-bit up counter : 3
|
8-bit up counter : 2
|
15-bit up counter : 2
|
# Registers : 205
|
# Registers : 206
|
Flip-Flops : 205
|
Flip-Flops : 206
|
# Comparators : 14
|
# Comparators : 14
|
4-bit comparator greater : 8
|
4-bit comparator greater : 8
|
6-bit comparator equal : 1
|
6-bit comparator equal : 1
|
6-bit comparator not equal : 2
|
6-bit comparator not equal : 2
|
8-bit comparator equal : 1
|
8-bit comparator equal : 1
|
8-bit comparator not equal : 2
|
8-bit comparator not equal : 2
|
# Multiplexers : 46
|
# Multiplexers : 47
|
1-bit 2-to-1 multiplexer : 20
|
1-bit 2-to-1 multiplexer : 21
|
4-bit 2-to-1 multiplexer : 12
|
4-bit 2-to-1 multiplexer : 12
|
8-bit 2-to-1 multiplexer : 14
|
8-bit 2-to-1 multiplexer : 14
|
# FSMs : 3
|
# FSMs : 3
|
|
|
=========================================================================
|
=========================================================================
|
| Line 492... |
Line 496... |
You should achieve better results by setting this init to 1.
|
You should achieve better results by setting this init to 1.
|
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_4 hinder the constant cleaning in the block spi_master_atlys_top.
|
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_4 hinder the constant cleaning in the block spi_master_atlys_top.
|
You should achieve better results by setting this init to 1.
|
You should achieve better results by setting this init to 1.
|
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top.
|
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top.
|
You should achieve better results by setting this init to 1.
|
You should achieve better results by setting this init to 1.
|
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_7 hinder the constant cleaning in the block spi_master_atlys_top.
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed :
|
You should achieve better results by setting this init to 1.
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed :
|
|
|
|
Optimizing unit ...
|
Optimizing unit ...
|
|
|
Optimizing unit ...
|
Optimizing unit ...
|
|
|
| Line 511... |
Line 514... |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed :
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed :
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following 2 FFs/Latches, which will be removed :
|
INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following 2 FFs/Latches, which will be removed :
|
|
|
Mapping all equations...
|
Mapping all equations...
|
Building and optimizing final netlist ...
|
Building and optimizing final netlist ...
|
| Line 528... |
Line 532... |
|
|
=========================================================================
|
=========================================================================
|
Final Register Report
|
Final Register Report
|
|
|
Macro Statistics
|
Macro Statistics
|
# Registers : 217
|
# Registers : 232
|
Flip-Flops : 217
|
Flip-Flops : 232
|
|
|
=========================================================================
|
=========================================================================
|
|
|
=========================================================================
|
=========================================================================
|
* Partition Report *
|
* Partition Report *
|
| Line 552... |
Line 556... |
|
|
Top Level Output File Name : spi_master_atlys_top.ngc
|
Top Level Output File Name : spi_master_atlys_top.ngc
|
|
|
Primitive and Black Box Usage:
|
Primitive and Black Box Usage:
|
------------------------------
|
------------------------------
|
# BELS : 205
|
# BELS : 259
|
# GND : 1
|
# GND : 1
|
# INV : 4
|
# INV : 4
|
# LUT1 : 14
|
# LUT1 : 28
|
# LUT2 : 4
|
# LUT2 : 3
|
# LUT3 : 28
|
# LUT3 : 26
|
# LUT4 : 17
|
# LUT4 : 17
|
# LUT5 : 55
|
# LUT5 : 62
|
# LUT6 : 47
|
# LUT6 : 55
|
# MUXCY : 14
|
# MUXCY : 28
|
# MUXF7 : 4
|
# MUXF7 : 4
|
# VCC : 1
|
# VCC : 1
|
# XORCY : 16
|
# XORCY : 30
|
# FlipFlops/Latches : 217
|
# FlipFlops/Latches : 232
|
# FD : 83
|
# FD : 97
|
# FD_1 : 1
|
# FD_1 : 1
|
# FDC : 8
|
# FDC : 8
|
# FDE : 111
|
# FDE : 111
|
|
# FDP_1 : 1
|
# FDR : 10
|
# FDR : 10
|
# FDRE : 4
|
# FDRE : 4
|
# Clock Buffers : 2
|
# Clock Buffers : 2
|
# BUFG : 1
|
# BUFG : 1
|
# BUFGP : 1
|
# BUFGP : 1
|
| Line 586... |
Line 591... |
|
|
Selected Device : 6slx45csg324-2
|
Selected Device : 6slx45csg324-2
|
|
|
|
|
Slice Logic Utilization:
|
Slice Logic Utilization:
|
Number of Slice Registers: 217 out of 54576 0%
|
Number of Slice Registers: 232 out of 54576 0%
|
Number of Slice LUTs: 169 out of 27288 0%
|
Number of Slice LUTs: 195 out of 27288 0%
|
Number used as Logic: 169 out of 27288 0%
|
Number used as Logic: 195 out of 27288 0%
|
|
|
Slice Logic Distribution:
|
Slice Logic Distribution:
|
Number of LUT Flip Flop pairs used: 274
|
Number of LUT Flip Flop pairs used: 301
|
Number with an unused Flip Flop: 57 out of 274 20%
|
Number with an unused Flip Flop: 69 out of 301 22%
|
Number with an unused LUT: 105 out of 274 38%
|
Number with an unused LUT: 106 out of 301 35%
|
Number of fully used LUT-FF pairs: 112 out of 274 40%
|
Number of fully used LUT-FF pairs: 126 out of 301 41%
|
Number of unique control sets: 23
|
Number of unique control sets: 23
|
|
|
IO Utilization:
|
IO Utilization:
|
Number of IOs: 63
|
Number of IOs: 63
|
Number of bonded IOBs: 63 out of 218 28%
|
Number of bonded IOBs: 63 out of 218 28%
|
| Line 625... |
Line 630... |
Clock Information:
|
Clock Information:
|
------------------
|
------------------
|
-----------------------------------+------------------------+-------+
|
-----------------------------------+------------------------+-------+
|
Clock Signal | Clock buffer(FF name) | Load |
|
Clock Signal | Clock buffer(FF name) | Load |
|
-----------------------------------+------------------------+-------+
|
-----------------------------------+------------------------+-------+
|
gclk_i | BUFGP | 189 |
|
gclk_i | BUFGP | 203 |
|
Inst_spi_master_port/spi_clk_reg | BUFG | 28 |
|
Inst_spi_master_port/spi_clk_reg | BUFG | 29 |
|
-----------------------------------+------------------------+-------+
|
-----------------------------------+------------------------+-------+
|
|
|
Asynchronous Control Signals Information:
|
Asynchronous Control Signals Information:
|
----------------------------------------
|
----------------------------------------
|
No asynchronous control signals found in this design
|
No asynchronous control signals found in this design
|
|
|
Timing Summary:
|
Timing Summary:
|
---------------
|
---------------
|
Speed Grade: -2
|
Speed Grade: -2
|
|
|
Minimum period: 5.283ns (Maximum Frequency: 189.286MHz)
|
Minimum period: 5.267ns (Maximum Frequency: 189.861MHz)
|
Minimum input arrival time before clock: 2.083ns
|
Minimum input arrival time before clock: 2.083ns
|
Maximum output required time after clock: 7.830ns
|
Maximum output required time after clock: 7.216ns
|
Maximum combinational path delay: No path found
|
Maximum combinational path delay: No path found
|
|
|
Timing Details:
|
Timing Details:
|
---------------
|
---------------
|
All values displayed in nanoseconds (ns)
|
All values displayed in nanoseconds (ns)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default period analysis for Clock 'gclk_i'
|
Timing constraint: Default period analysis for Clock 'gclk_i'
|
Clock period: 5.283ns (frequency: 189.286MHz)
|
Clock period: 5.267ns (frequency: 189.861MHz)
|
Total number of paths / destination ports: 1727 / 266
|
Total number of paths / destination ports: 2605 / 280
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Delay: 5.283ns (Levels of Logic = 4)
|
Delay: 5.267ns (Levels of Logic = 4)
|
Source: sw_reg_5 (FF)
|
Source: sw_reg_5 (FF)
|
Destination: btn_reg_0 (FF)
|
Destination: m_wr_st_reg_FSM_FFd4 (FF)
|
Source Clock: gclk_i rising
|
Source Clock: gclk_i rising
|
Destination Clock: gclk_i rising
|
Destination Clock: gclk_i rising
|
|
|
Data Path: sw_reg_5 to btn_reg_0
|
Data Path: sw_reg_5 to m_wr_st_reg_FSM_FFd4
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDE:C->Q 3 0.525 1.196 sw_reg_5 (sw_reg_5)
|
FDE:C->Q 3 0.525 1.196 sw_reg_5 (sw_reg_5)
|
LUT6:I1->O 2 0.254 0.834 _n038082 (_n038081)
|
LUT6:I1->O 2 0.254 0.834 _n038082 (_n038081)
|
LUT6:I4->O 3 0.250 0.766 _n038083 (_n0380)
|
LUT6:I4->O 8 0.250 0.944 _n038083 (_n0380)
|
LUT5:I4->O 6 0.254 0.876 _n0418_inv1_rstpot (_n0418_inv1_rstpot)
|
LUT5:I4->O 1 0.254 0.682 m_wr_st_reg_FSM_FFd2-In1 (m_wr_st_reg_FSM_FFd2-In1)
|
LUT3:I2->O 1 0.254 0.000 btn_reg_0_dpot (btn_reg_0_dpot)
|
LUT6:I5->O 1 0.254 0.000 m_wr_st_reg_FSM_FFd2-In2 (m_wr_st_reg_FSM_FFd2-In)
|
FDE:D 0.074 btn_reg_0
|
FDR:D 0.074 m_wr_st_reg_FSM_FFd2
|
----------------------------------------
|
----------------------------------------
|
Total 5.283ns (1.611ns logic, 3.672ns route)
|
Total 5.267ns (1.611ns logic, 3.656ns route)
|
(30.5% logic, 69.5% route)
|
(30.6% logic, 69.4% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg'
|
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg'
|
Clock period: 4.344ns (frequency: 230.203MHz)
|
Clock period: 4.344ns (frequency: 230.203MHz)
|
Total number of paths / destination ports: 214 / 36
|
Total number of paths / destination ports: 214 / 36
|
| Line 687... |
Line 692... |
Data Path: Inst_spi_slave_port/state_reg_1_1 to Inst_spi_slave_port/tx_bit_reg
|
Data Path: Inst_spi_slave_port/state_reg_1_1 to Inst_spi_slave_port/tx_bit_reg
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDC:C->Q 2 0.525 1.156 Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1)
|
FDC:C->Q 2 0.525 1.156 Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1)
|
LUT6:I1->O 1 0.254 0.000 Inst_spi_slave_port/tx_bit_next3_F (N14)
|
LUT6:I1->O 1 0.254 0.000 Inst_spi_slave_port/tx_bit_next3_F (N10)
|
MUXF7:I0->O 1 0.163 0.000 Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next)
|
MUXF7:I0->O 1 0.163 0.000 Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next)
|
FD_1:D 0.074 Inst_spi_slave_port/tx_bit_reg
|
FD_1:D 0.074 Inst_spi_slave_port/tx_bit_reg
|
----------------------------------------
|
----------------------------------------
|
Total 2.172ns (1.016ns logic, 1.156ns route)
|
Total 2.172ns (1.016ns logic, 1.156ns route)
|
(46.8% logic, 53.2% route)
|
(46.8% logic, 53.2% route)
|
| Line 715... |
Line 720... |
Total 2.083ns (1.402ns logic, 0.681ns route)
|
Total 2.083ns (1.402ns logic, 0.681ns route)
|
(67.3% logic, 32.7% route)
|
(67.3% logic, 32.7% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
|
Total number of paths / destination ports: 41 / 31
|
Total number of paths / destination ports: 37 / 31
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 7.663ns (Levels of Logic = 4)
|
Offset: 7.216ns (Levels of Logic = 3)
|
Source: Inst_spi_master_port/ssel_ena_reg (FF)
|
Source: Inst_spi_master_port/state_reg_2 (FF)
|
Destination: spi_miso_o (PAD)
|
Destination: spi_mosi_o (PAD)
|
Source Clock: gclk_i rising
|
Source Clock: gclk_i rising
|
|
|
Data Path: Inst_spi_master_port/ssel_ena_reg to spi_miso_o
|
Data Path: Inst_spi_master_port/state_reg_2 to spi_mosi_o
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDE:C->Q 5 0.525 1.271 Inst_spi_master_port/ssel_ena_reg (Inst_spi_master_port/ssel_ena_reg)
|
FDRE:C->Q 20 0.525 1.394 Inst_spi_master_port/state_reg_2 (Inst_spi_master_port/state_reg_2)
|
LUT5:I0->O 1 0.254 0.682 Inst_spi_slave_port/spi_miso_o2 (Inst_spi_slave_port/spi_miso_o1)
|
LUT2:I0->O 2 0.250 1.156 Inst_spi_master_port/spi_mosi_o_SW0 (N0)
|
LUT6:I5->O 2 0.254 0.834 Inst_spi_slave_port/spi_miso_o3 (Inst_spi_slave_port/spi_miso_o2)
|
LUT6:I1->O 2 0.254 0.725 Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)
|
LUT3:I1->O 1 0.250 0.681 Inst_spi_slave_port/spi_miso_o4 (spi_miso_o_OBUF)
|
OBUF:I->O 2.912 spi_mosi_o_OBUF (spi_mosi_o)
|
OBUF:I->O 2.912 spi_miso_o_OBUF (spi_miso_o)
|
|
----------------------------------------
|
----------------------------------------
|
Total 7.663ns (4.195ns logic, 3.468ns route)
|
Total 7.216ns (3.941ns logic, 3.275ns route)
|
(54.7% logic, 45.3% route)
|
(54.6% logic, 45.4% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg'
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg'
|
Total number of paths / destination ports: 25 / 14
|
Total number of paths / destination ports: 19 / 18
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 7.830ns (Levels of Logic = 4)
|
Offset: 5.307ns (Levels of Logic = 2)
|
Source: Inst_spi_slave_port/state_reg_0 (FF)
|
Source: Inst_spi_slave_port/preload_miso (FF)
|
Destination: spi_miso_o (PAD)
|
Destination: spi_miso_o (PAD)
|
Source Clock: Inst_spi_master_port/spi_clk_reg rising
|
Source Clock: Inst_spi_master_port/spi_clk_reg falling
|
|
|
Data Path: Inst_spi_slave_port/state_reg_0 to spi_miso_o
|
Data Path: Inst_spi_slave_port/preload_miso to spi_miso_o
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDC:C->Q 22 0.525 1.442 Inst_spi_slave_port/state_reg_0 (Inst_spi_slave_port/state_reg_0)
|
FDP_1:C->Q 2 0.525 0.954 Inst_spi_slave_port/preload_miso (Inst_spi_slave_port/preload_miso)
|
LUT5:I3->O 1 0.250 0.682 Inst_spi_slave_port/spi_miso_o2 (Inst_spi_slave_port/spi_miso_o1)
|
LUT3:I0->O 1 0.235 0.681 Inst_spi_slave_port/Mmux_spi_miso_o11 (spi_miso_o_OBUF)
|
LUT6:I5->O 2 0.254 0.834 Inst_spi_slave_port/spi_miso_o3 (Inst_spi_slave_port/spi_miso_o2)
|
|
LUT3:I1->O 1 0.250 0.681 Inst_spi_slave_port/spi_miso_o4 (spi_miso_o_OBUF)
|
|
OBUF:I->O 2.912 spi_miso_o_OBUF (spi_miso_o)
|
OBUF:I->O 2.912 spi_miso_o_OBUF (spi_miso_o)
|
----------------------------------------
|
----------------------------------------
|
Total 7.830ns (4.191ns logic, 3.639ns route)
|
Total 5.307ns (3.672ns logic, 1.635ns route)
|
(53.5% logic, 46.5% route)
|
(69.2% logic, 30.8% route)
|
|
|
=========================================================================
|
=========================================================================
|
|
|
Cross Clock Domains Report:
|
Cross Clock Domains Report:
|
--------------------------
|
--------------------------
|
| Line 767... |
Line 769... |
Clock to Setup on destination clock Inst_spi_master_port/spi_clk_reg
|
Clock to Setup on destination clock Inst_spi_master_port/spi_clk_reg
|
--------------------------------+---------+---------+---------+---------+
|
--------------------------------+---------+---------+---------+---------+
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
--------------------------------+---------+---------+---------+---------+
|
--------------------------------+---------+---------+---------+---------+
|
Inst_spi_master_port/spi_clk_reg| 3.706| | 2.262| |
|
Inst_spi_master_port/spi_clk_reg| 3.682| | 2.224| |
|
gclk_i | 4.633| | 2.169| |
|
gclk_i | 4.633| | 3.198| |
|
--------------------------------+---------+---------+---------+---------+
|
--------------------------------+---------+---------+---------+---------+
|
|
|
Clock to Setup on destination clock gclk_i
|
Clock to Setup on destination clock gclk_i
|
--------------------------------+---------+---------+---------+---------+
|
--------------------------------+---------+---------+---------+---------+
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
--------------------------------+---------+---------+---------+---------+
|
--------------------------------+---------+---------+---------+---------+
|
Inst_spi_master_port/spi_clk_reg| 4.416| 3.782| | |
|
Inst_spi_master_port/spi_clk_reg| 2.078| 1.855| | |
|
gclk_i | 5.283| | | |
|
gclk_i | 5.267| | | |
|
--------------------------------+---------+---------+---------+---------+
|
--------------------------------+---------+---------+---------+---------+
|
|
|
=========================================================================
|
=========================================================================
|
|
|
|
|
Total REAL time to Xst completion: 8.00 secs
|
Total REAL time to Xst completion: 6.00 secs
|
Total CPU time to Xst completion: 7.33 secs
|
Total CPU time to Xst completion: 6.29 secs
|
|
|
-->
|
-->
|
|
|
Total memory usage is 178696 kilobytes
|
Total memory usage is 188108 kilobytes
|
|
|
Number of errors : 0 ( 0 filtered)
|
Number of errors : 0 ( 0 filtered)
|
Number of warnings : 29 ( 0 filtered)
|
Number of warnings : 26 ( 0 filtered)
|
Number of infos : 22 ( 0 filtered)
|
Number of infos : 24 ( 0 filtered)
|
|
|
