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Release 13.1 Trace (nt)
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Release 13.1 Trace (nt)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
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C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
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3 -fastpaths -xml spi_master_atlys_top.twx spi_master_atlys_top.ncd -o
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3 -fastpaths -xml spi_master_atlys_top.twx spi_master_atlys_top.ncd -o
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spi_master_atlys_top.twr spi_master_atlys_top.pcf -ucf spi_master_atlys.ucf
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spi_master_atlys_top.twr spi_master_atlys_top.pcf -ucf spi_master_atlys.ucf
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Design file: spi_master_atlys_top.ncd
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Design file: spi_master_atlys_top.ncd
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Physical constraint file: spi_master_atlys_top.pcf
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Physical constraint file: spi_master_atlys_top.pcf
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Device,package,speed: xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07)
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Device,package,speed: xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07)
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Report level: verbose report
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Report level: verbose report
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Environment Variable Effect
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Environment Variable Effect
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-------------------- ------
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-------------------- ------
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NONE No environment variables were set
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NONE No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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please see the device datasheet.
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Data Sheet report:
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Data Sheet report:
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-----------------
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-----------------
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All values displayed in nanoseconds (ns)
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All values displayed in nanoseconds (ns)
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Setup/Hold to clock gclk_i
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Setup/Hold to clock gclk_i
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------------+------------+------------+------------+------------+------------------+--------+
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------------+------------+------------+------------+------------+------------------+--------+
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|Max Setup to| Process |Max Hold to | Process | | Clock |
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|Max Setup to| Process |Max Hold to | Process | | Clock |
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Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
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Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
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------------+------------+------------+------------+------------+------------------+--------+
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------------+------------+------------+------------+------------+------------------+--------+
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btn_i<0> | 3.278(R)| SLOW | -1.955(R)| FAST |gclk_i_BUFGP | 0.000|
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btn_i<0> | 3.220(R)| SLOW | -1.908(R)| FAST |gclk_i_BUFGP | 0.000|
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btn_i<1> | 2.687(R)| SLOW | -1.446(R)| FAST |gclk_i_BUFGP | 0.000|
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btn_i<1> | 2.732(R)| SLOW | -1.473(R)| FAST |gclk_i_BUFGP | 0.000|
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btn_i<2> | 2.472(R)| SLOW | -1.378(R)| FAST |gclk_i_BUFGP | 0.000|
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btn_i<2> | 2.624(R)| SLOW | -1.423(R)| FAST |gclk_i_BUFGP | 0.000|
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btn_i<3> | 2.485(R)| SLOW | -1.363(R)| FAST |gclk_i_BUFGP | 0.000|
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btn_i<3> | 2.466(R)| SLOW | -1.367(R)| SLOW |gclk_i_BUFGP | 0.000|
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btn_i<4> | 3.029(R)| SLOW | -1.604(R)| FAST |gclk_i_BUFGP | 0.000|
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btn_i<4> | 2.808(R)| SLOW | -1.482(R)| FAST |gclk_i_BUFGP | 0.000|
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btn_i<5> | 2.674(R)| SLOW | -1.430(R)| SLOW |gclk_i_BUFGP | 0.000|
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btn_i<5> | 2.631(R)| SLOW | -1.435(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<0> | 4.100(R)| SLOW | -2.174(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<0> | 4.138(R)| SLOW | -2.205(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<1> | 5.263(R)| SLOW | -2.981(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<1> | 5.757(R)| SLOW | -3.265(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<2> | 5.340(R)| SLOW | -2.970(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<2> | 5.825(R)| SLOW | -3.246(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<3> | 4.839(R)| SLOW | -2.685(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<3> | 4.946(R)| SLOW | -2.785(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<4> | 3.689(R)| SLOW | -2.001(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<4> | 3.431(R)| SLOW | -1.904(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<5> | 4.210(R)| SLOW | -2.310(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<5> | 3.569(R)| SLOW | -2.000(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<6> | 4.396(R)| SLOW | -2.450(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<6> | 3.411(R)| SLOW | -1.943(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<7> | 4.807(R)| SLOW | -2.644(R)| FAST |gclk_i_BUFGP | 0.000|
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sw_i<7> | 5.265(R)| SLOW | -2.971(R)| FAST |gclk_i_BUFGP | 0.000|
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------------+------------+------------+------------+------------+------------------+--------+
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------------+------------+------------+------------+------------+------------------+--------+
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Clock gclk_i to Pad
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Clock gclk_i to Pad
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
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|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
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Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
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Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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dbg_o<4> | 10.189(R)| SLOW | 4.245(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<4> | 9.886(R)| SLOW | 4.102(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<5> | 10.661(R)| SLOW | 4.525(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<5> | 9.856(R)| SLOW | 4.079(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<7> | 10.584(R)| SLOW | 4.515(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<7> | 10.279(R)| SLOW | 4.343(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<8> | 10.546(R)| SLOW | 4.517(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<8> | 10.485(R)| SLOW | 4.438(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<9> | 10.444(R)| SLOW | 4.424(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<9> | 10.661(R)| SLOW | 4.583(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<10> | 11.747(R)| SLOW | 5.263(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<10> | 10.595(R)| SLOW | 4.516(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<11> | 10.850(R)| SLOW | 4.663(R)| FAST |gclk_i_BUFGP | 0.000|
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dbg_o<11> | 10.797(R)| SLOW | 4.632(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<0> | 9.978(R)| SLOW | 4.140(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<0> | 10.127(R)| SLOW | 4.227(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<1> | 9.999(R)| SLOW | 4.146(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<1> | 9.955(R)| SLOW | 4.135(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<2> | 9.969(R)| SLOW | 4.128(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<2> | 10.096(R)| SLOW | 4.211(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<3> | 9.554(R)| SLOW | 3.890(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<3> | 9.531(R)| SLOW | 3.887(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<4> | 10.087(R)| SLOW | 4.246(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<4> | 10.129(R)| SLOW | 4.244(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<5> | 16.607(R)| SLOW | 8.007(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<5> | 16.930(R)| SLOW | 8.194(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<6> | 11.948(R)| SLOW | 5.282(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<6> | 12.027(R)| SLOW | 5.407(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<7> | 11.126(R)| SLOW | 4.792(R)| FAST |gclk_i_BUFGP | 0.000|
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led_o<7> | 11.196(R)| SLOW | 4.818(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<0> | 9.589(R)| SLOW | 3.927(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<0> | 9.636(R)| SLOW | 3.930(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<1> | 9.834(R)| SLOW | 4.096(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<1> | 9.683(R)| SLOW | 3.987(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<2> | 9.806(R)| SLOW | 4.063(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<2> | 9.651(R)| SLOW | 3.945(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<3> | 9.369(R)| SLOW | 3.801(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<3> | 9.718(R)| SLOW | 4.091(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<4> | 9.464(R)| SLOW | 3.837(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<4> | 9.623(R)| SLOW | 4.055(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<5> | 9.704(R)| SLOW | 4.008(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<5> | 9.875(R)| SLOW | 4.135(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<6> | 9.672(R)| SLOW | 3.966(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<6> | 9.742(R)| SLOW | 4.088(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<7> | 9.539(R)| SLOW | 3.912(R)| FAST |gclk_i_BUFGP | 0.000|
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m_do_o<7> | 9.568(R)| SLOW | 4.000(R)| FAST |gclk_i_BUFGP | 0.000|
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m_state_o<0>| 11.606(R)| SLOW | 5.188(R)| FAST |gclk_i_BUFGP | 0.000|
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m_state_o<0>| 11.544(R)| SLOW | 5.167(R)| FAST |gclk_i_BUFGP | 0.000|
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m_state_o<1>| 11.499(R)| SLOW | 5.055(R)| FAST |gclk_i_BUFGP | 0.000|
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m_state_o<1>| 11.702(R)| SLOW | 5.283(R)| FAST |gclk_i_BUFGP | 0.000|
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m_state_o<2>| 11.467(R)| SLOW | 5.046(R)| FAST |gclk_i_BUFGP | 0.000|
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m_state_o<2>| 11.667(R)| SLOW | 5.272(R)| FAST |gclk_i_BUFGP | 0.000|
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m_state_o<3>| 11.607(R)| SLOW | 5.144(R)| FAST |gclk_i_BUFGP | 0.000|
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m_state_o<3>| 11.707(R)| SLOW | 5.314(R)| FAST |gclk_i_BUFGP | 0.000|
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spi_miso_o | 13.517(R)| SLOW | 5.528(R)| FAST |gclk_i_BUFGP | 0.000|
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spi_miso_o | 11.814(R)| SLOW | 5.115(R)| FAST |gclk_i_BUFGP | 0.000|
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spi_mosi_o | 13.405(R)| SLOW | 5.552(R)| FAST |gclk_i_BUFGP | 0.000|
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spi_mosi_o | 13.768(R)| SLOW | 5.317(R)| FAST |gclk_i_BUFGP | 0.000|
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spi_sck_o | 11.665(R)| SLOW | 5.240(R)| FAST |gclk_i_BUFGP | 0.000|
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spi_sck_o | 11.645(R)| SLOW | 5.148(R)| FAST |gclk_i_BUFGP | 0.000|
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spi_ssel_o | 12.854(R)| SLOW | 5.876(R)| FAST |gclk_i_BUFGP | 0.000|
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spi_ssel_o | 12.580(R)| SLOW | 5.649(R)| FAST |gclk_i_BUFGP | 0.000|
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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Clock to Setup on destination clock gclk_i
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Clock to Setup on destination clock gclk_i
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---------------+---------+---------+---------+---------+
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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---------------+---------+---------+---------+---------+
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gclk_i | 5.299| | | |
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gclk_i | 4.888| | | |
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---------------+---------+---------+---------+---------+
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---------------+---------+---------+---------+---------+
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Analysis completed Wed Aug 10 22:57:08 2011
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Analysis completed Mon Aug 29 00:08:54 2011
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Trace Settings:
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Trace Settings:
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-------------------------
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-------------------------
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Trace Settings
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Trace Settings
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Peak Memory Usage: 180 MB
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Peak Memory Usage: 177 MB
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