OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top_map.map] - Diff between revs 20 and 22

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 20 Rev 22
Line 10... Line 10...
spi_master_atlys_top.pcf
spi_master_atlys_top.pcf
Target Device  : xc6slx45
Target Device  : xc6slx45
Target Package : csg324
Target Package : csg324
Target Speed   : -2
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Wed Aug 10 22:56:29 2011
Mapped Date    : Mon Aug 29 00:08:18 2011
 
 
Running global optimization...
Running global optimization...
Mapping design into LUTs...
Mapping design into LUTs...
Running directed packing...
Running directed packing...
Running delay-based LUT packing...
Running delay-based LUT packing...
Updating timing models...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
   (.mrp).
Running timing-driven placement...
Running timing-driven placement...
Total REAL time at the beginning of Placer: 10 secs
Total REAL time at the beginning of Placer: 9 secs
Total CPU  time at the beginning of Placer: 9 secs
Total CPU  time at the beginning of Placer: 9 secs
 
 
Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:542d7d4b) REAL time: 11 secs
Phase 1.1  Initial Placement Analysis (Checksum:7388cd6e) REAL time: 10 secs
 
 
Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 43 are locked
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 47 are locked
   and 20 are not locked. If you would like to print the names of these IOs,
   and 16 are not locked. If you would like to print the names of these IOs,
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7  Design Feasibility Check (Checksum:542d7d4b) REAL time: 11 secs
Phase 2.7  Design Feasibility Check (Checksum:7388cd6e) REAL time: 10 secs
 
 
Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:542d7d4b) REAL time: 11 secs
Phase 3.31  Local Placement Optimization (Checksum:7388cd6e) REAL time: 10 secs
 
 
Phase 4.2  Initial Placement for Architecture Specific Features
Phase 4.2  Initial Placement for Architecture Specific Features
...
...
Phase 4.2  Initial Placement for Architecture Specific Features
Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:23369eb) REAL time: 16 secs
(Checksum:e9015cfe) REAL time: 14 secs
 
 
Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:23369eb) REAL time: 16 secs
Phase 5.36  Local Placement Optimization (Checksum:e9015cfe) REAL time: 14 secs
 
 
Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:23369eb) REAL time: 16 secs
Phase 6.30  Global Clock Region Assignment (Checksum:e9015cfe) REAL time: 14 secs
 
 
Phase 7.3  Local Placement Optimization
Phase 7.3  Local Placement Optimization
...
...
Phase 7.3  Local Placement Optimization (Checksum:c4747df0) REAL time: 16 secs
Phase 7.3  Local Placement Optimization (Checksum:fcc976fb) REAL time: 15 secs
 
 
Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:c4747df0) REAL time: 16 secs
Phase 8.5  Local Placement Optimization (Checksum:fcc976fb) REAL time: 15 secs
 
 
Phase 9.8  Global Placement
Phase 9.8  Global Placement
...........
..
.....
..
Phase 9.8  Global Placement (Checksum:55e2a6f9) REAL time: 17 secs
Phase 9.8  Global Placement (Checksum:4a08930d) REAL time: 15 secs
 
 
Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:55e2a6f9) REAL time: 17 secs
Phase 10.5  Local Placement Optimization (Checksum:4a08930d) REAL time: 15 secs
 
 
Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:402bf1c7) REAL time: 18 secs
Phase 11.18  Placement Optimization (Checksum:1a1797e0) REAL time: 16 secs
 
 
Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:402bf1c7) REAL time: 18 secs
Phase 12.5  Local Placement Optimization (Checksum:1a1797e0) REAL time: 16 secs
 
 
Phase 13.34  Placement Validation
Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:55d3da5) REAL time: 18 secs
Phase 13.34  Placement Validation (Checksum:bc560c6c) REAL time: 16 secs
 
 
Total REAL time to Placer completion: 18 secs
Total REAL time to Placer completion: 16 secs
Total CPU  time to Placer completion: 16 secs
Total CPU  time to Placer completion: 16 secs
Running post-placement packing...
Running post-placement packing...
Writing output files...
Writing output files...
 
 
Design Summary
Design Summary
Line 82... Line 82...
 
 
Design Summary:
Design Summary:
Number of errors:      0
Number of errors:      0
Number of warnings:    0
Number of warnings:    0
Slice Logic Utilization:
Slice Logic Utilization:
  Number of Slice Registers:                   209 out of  54,576    1%
  Number of Slice Registers:                   224 out of  54,576    1%
    Number used as Flip Flops:                 209
    Number used as Flip Flops:                 224
    Number used as Latches:                      0
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        145 out of  27,288    1%
  Number of Slice LUTs:                        177 out of  27,288    1%
    Number used as logic:                      127 out of  27,288    1%
    Number used as logic:                      167 out of  27,288    1%
      Number using O6 output only:              75
      Number using O6 output only:             112
      Number using O5 output only:              13
      Number using O5 output only:              28
      Number using O5 and O6:                   39
      Number using O5 and O6:                   27
      Number used as ROM:                        0
      Number used as ROM:                        0
    Number used as Memory:                       4 out of   6,408    1%
    Number used as Memory:                       4 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             4
      Number used as Shift Register:             4
        Number using O6 output only:             4
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 output only:             0
        Number using O5 and O6:                  0
        Number using O5 and O6:                  0
    Number used exclusively as route-thrus:     14
    Number used exclusively as route-thrus:      6
      Number with same-slice register load:     12
      Number with same-slice register load:      4
      Number with same-slice carry load:         2
      Number with same-slice carry load:         2
      Number with other load:                    0
      Number with other load:                    0
 
 
Slice Logic Distribution:
Slice Logic Distribution:
  Number of occupied Slices:                    91 out of   6,822    1%
  Number of occupied Slices:                   102 out of   6,822    1%
  Number of LUT Flip Flop pairs used:          225
  Number of LUT Flip Flop pairs used:          272
    Number with an unused Flip Flop:            49 out of     225   21%
    Number with an unused Flip Flop:            64 out of     272   23%
    Number with an unused LUT:                  80 out of     225   35%
    Number with an unused LUT:                  95 out of     272   34%
    Number of fully used LUT-FF pairs:          96 out of     225   42%
    Number of fully used LUT-FF pairs:         113 out of     272   41%
    Number of unique control sets:              25
    Number of unique control sets:              26
    Number of slice register sites lost
    Number of slice register sites lost
      to control set restrictions:              59 out of  54,576    1%
      to control set restrictions:              68 out of  54,576    1%
 
 
  A LUT Flip Flop pair for this architecture represents one LUT paired with
  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  over-mapped for a non-slice resource or if Placement fails.
 
 
IO Utilization:
IO Utilization:
  Number of bonded IOBs:                        63 out of     218   28%
  Number of bonded IOBs:                        63 out of     218   28%
    Number of LOCed IOBs:                       43 out of      63   68%
    Number of LOCed IOBs:                       47 out of      63   74%
 
 
Specific Feature Utilization:
Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
Line 150... Line 150...
  Number of PLL_ADVs:                            0 out of       4    0%
  Number of PLL_ADVs:                            0 out of       4    0%
  Number of PMVs:                                0 out of       1    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%
 
 
Average Fanout of Non-Clock Nets:                2.81
Average Fanout of Non-Clock Nets:                3.18
 
 
Peak Memory Usage:  303 MB
Peak Memory Usage:  298 MB
Total REAL time to MAP completion:  19 secs
Total REAL time to MAP completion:  17 secs
Total CPU time to MAP completion (all processors):   17 secs
Total CPU time to MAP completion (all processors):   17 secs
 
 
Mapping completed.
Mapping completed.
See MAP report file "spi_master_atlys_top_map.mrp" for details.
See MAP report file "spi_master_atlys_top_map.mrp" for details.

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.