Line 10... |
Line 10... |
spi_master_atlys_top.pcf
|
spi_master_atlys_top.pcf
|
Target Device : xc6slx45
|
Target Device : xc6slx45
|
Target Package : csg324
|
Target Package : csg324
|
Target Speed : -2
|
Target Speed : -2
|
Mapper Version : spartan6 -- $Revision: 1.55 $
|
Mapper Version : spartan6 -- $Revision: 1.55 $
|
Mapped Date : Mon Aug 29 00:08:18 2011
|
Mapped Date : Thu Sep 01 13:07:11 2011
|
|
|
Design Summary
|
Design Summary
|
--------------
|
--------------
|
Number of errors: 0
|
Number of errors: 0
|
Number of warnings: 0
|
Number of warnings: 0
|
Slice Logic Utilization:
|
Slice Logic Utilization:
|
Number of Slice Registers: 224 out of 54,576 1%
|
Number of Slice Registers: 210 out of 54,576 1%
|
Number used as Flip Flops: 224
|
Number used as Flip Flops: 210
|
Number used as Latches: 0
|
Number used as Latches: 0
|
Number used as Latch-thrus: 0
|
Number used as Latch-thrus: 0
|
Number used as AND/OR logics: 0
|
Number used as AND/OR logics: 0
|
Number of Slice LUTs: 177 out of 27,288 1%
|
Number of Slice LUTs: 143 out of 27,288 1%
|
Number used as logic: 167 out of 27,288 1%
|
Number used as logic: 129 out of 27,288 1%
|
Number using O6 output only: 112
|
Number using O6 output only: 79
|
Number using O5 output only: 28
|
Number using O5 output only: 15
|
Number using O5 and O6: 27
|
Number using O5 and O6: 35
|
Number used as ROM: 0
|
Number used as ROM: 0
|
Number used as Memory: 4 out of 6,408 1%
|
Number used as Memory: 4 out of 6,408 1%
|
Number used as Dual Port RAM: 0
|
Number used as Dual Port RAM: 0
|
Number used as Single Port RAM: 0
|
Number used as Single Port RAM: 0
|
Number used as Shift Register: 4
|
Number used as Shift Register: 4
|
Number using O6 output only: 4
|
Number using O6 output only: 4
|
Number using O5 output only: 0
|
Number using O5 output only: 0
|
Number using O5 and O6: 0
|
Number using O5 and O6: 0
|
Number used exclusively as route-thrus: 6
|
Number used exclusively as route-thrus: 10
|
Number with same-slice register load: 4
|
Number with same-slice register load: 8
|
Number with same-slice carry load: 2
|
Number with same-slice carry load: 2
|
Number with other load: 0
|
Number with other load: 0
|
|
|
Slice Logic Distribution:
|
Slice Logic Distribution:
|
Number of occupied Slices: 102 out of 6,822 1%
|
Number of occupied Slices: 91 out of 6,822 1%
|
Number of LUT Flip Flop pairs used: 272
|
Number of LUT Flip Flop pairs used: 231
|
Number with an unused Flip Flop: 64 out of 272 23%
|
Number with an unused Flip Flop: 46 out of 231 19%
|
Number with an unused LUT: 95 out of 272 34%
|
Number with an unused LUT: 88 out of 231 38%
|
Number of fully used LUT-FF pairs: 113 out of 272 41%
|
Number of fully used LUT-FF pairs: 97 out of 231 41%
|
Number of unique control sets: 26
|
Number of unique control sets: 27
|
Number of slice register sites lost
|
Number of slice register sites lost
|
to control set restrictions: 68 out of 54,576 1%
|
to control set restrictions: 74 out of 54,576 1%
|
|
|
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
one Flip Flop within a slice. A control set is a unique combination of
|
one Flip Flop within a slice. A control set is a unique combination of
|
clock, reset, set, and enable signals for a registered element.
|
clock, reset, set, and enable signals for a registered element.
|
The Slice Logic Distribution report is not meaningful if the design is
|
The Slice Logic Distribution report is not meaningful if the design is
|
over-mapped for a non-slice resource or if Placement fails.
|
over-mapped for a non-slice resource or if Placement fails.
|
|
|
IO Utilization:
|
IO Utilization:
|
Number of bonded IOBs: 63 out of 218 28%
|
Number of bonded IOBs: 64 out of 218 29%
|
Number of LOCed IOBs: 47 out of 63 74%
|
Number of LOCed IOBs: 46 out of 64 71%
|
|
|
Specific Feature Utilization:
|
Specific Feature Utilization:
|
Number of RAMB16BWERs: 0 out of 116 0%
|
Number of RAMB16BWERs: 0 out of 116 0%
|
Number of RAMB8BWERs: 0 out of 232 0%
|
Number of RAMB8BWERs: 0 out of 232 0%
|
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
|
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
|
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
|
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
|
Number of BUFG/BUFGMUXs: 2 out of 16 12%
|
Number of BUFG/BUFGMUXs: 3 out of 16 18%
|
Number used as BUFGs: 2
|
Number used as BUFGs: 3
|
Number used as BUFGMUX: 0
|
Number used as BUFGMUX: 0
|
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
|
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
|
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
|
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
|
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
|
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
|
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
|
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
|
Line 85... |
Line 85... |
Number of PLL_ADVs: 0 out of 4 0%
|
Number of PLL_ADVs: 0 out of 4 0%
|
Number of PMVs: 0 out of 1 0%
|
Number of PMVs: 0 out of 1 0%
|
Number of STARTUPs: 0 out of 1 0%
|
Number of STARTUPs: 0 out of 1 0%
|
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
|
|
Average Fanout of Non-Clock Nets: 3.18
|
Average Fanout of Non-Clock Nets: 2.86
|
|
|
Peak Memory Usage: 298 MB
|
Peak Memory Usage: 301 MB
|
Total REAL time to MAP completion: 17 secs
|
Total REAL time to MAP completion: 17 secs
|
Total CPU time to MAP completion (all processors): 17 secs
|
Total CPU time to MAP completion (all processors): 17 secs
|
|
|
Table of Contents
|
Table of Contents
|
-----------------
|
-----------------
|
Line 128... |
Line 128... |
removed :
|
removed :
|
INFO:Xst:2261 - The FF/Latch in Unit
|
INFO:Xst:2261 - The FF/Latch in Unit
|
is equivalent to the following 2 FFs/Latches, which
|
is equivalent to the following 2 FFs/Latches, which
|
will be removed :
|
will be removed :
|
|
|
INFO:LIT:243 - Logical network gclk_i_BUFGP/N2 has no load.
|
INFO:LIT:243 - Logical network pclk_i_BUFGP/N2 has no load.
|
INFO:LIT:243 - Logical network gclk_i_BUFGP/N3 has no load.
|
INFO:LIT:243 - Logical network pclk_i_BUFGP/N3 has no load.
|
|
INFO:LIT:243 - Logical network sclk_i_BUFGP/N2 has no load.
|
|
INFO:LIT:243 - Logical network sclk_i_BUFGP/N3 has no load.
|
INFO:MapLib:562 - No environment variables are currently set.
|
INFO:MapLib:562 - No environment variables are currently set.
|
INFO:LIT:244 - All of the single ended outputs in this design are using slew
|
INFO:LIT:244 - All of the single ended outputs in this design are using slew
|
rate limited output drivers. The delay on speed critical single ended outputs
|
rate limited output drivers. The delay on speed critical single ended outputs
|
can be dramatically reduced by designating them as fast outputs.
|
can be dramatically reduced by designating them as fast outputs.
|
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
|
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
|
0.000 to 85.000 Celsius)
|
0.000 to 85.000 Celsius)
|
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
|
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
|
1.260 Volts)
|
1.260 Volts)
|
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
|
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
|
(.mrp).
|
(.mrp).
|
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 47 are locked
|
INFO:Place:834 - Only a subset of IOs are locked. Out of 64 IOs, 46 are locked
|
and 16 are not locked. If you would like to print the names of these IOs,
|
and 18 are not locked. If you would like to print the names of these IOs,
|
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
|
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
|
INFO:Pack:1650 - Map created a placed design.
|
INFO:Pack:1650 - Map created a placed design.
|
|
|
Section 4 - Removed Logic Summary
|
Section 4 - Removed Logic Summary
|
---------------------------------
|
---------------------------------
|
2 block(s) removed
|
4 block(s) removed
|
2 block(s) optimized away
|
2 block(s) optimized away
|
2 signal(s) removed
|
4 signal(s) removed
|
87 Block(s) redundant
|
58 Block(s) redundant
|
|
|
Section 5 - Removed Logic
|
Section 5 - Removed Logic
|
-------------------------
|
-------------------------
|
|
|
The trimmed logic report below shows the logic removed from your design due to
|
The trimmed logic report below shows the logic removed from your design due to
|
Line 165... |
Line 167... |
|
|
To quickly locate the original cause for the removal of a chain of logic, look
|
To quickly locate the original cause for the removal of a chain of logic, look
|
above the place where that logic is listed in the trimming report, then locate
|
above the place where that logic is listed in the trimming report, then locate
|
the lines that are least indented (begin at the leftmost edge).
|
the lines that are least indented (begin at the leftmost edge).
|
|
|
The signal "gclk_i_BUFGP/N2" is sourceless and has been removed.
|
The signal "pclk_i_BUFGP/N2" is sourceless and has been removed.
|
The signal "gclk_i_BUFGP/N3" is sourceless and has been removed.
|
The signal "pclk_i_BUFGP/N3" is sourceless and has been removed.
|
Unused block "gclk_i_BUFGP/XST_GND" (ZERO) removed.
|
The signal "sclk_i_BUFGP/N2" is sourceless and has been removed.
|
Unused block "gclk_i_BUFGP/XST_VCC" (ONE) removed.
|
The signal "sclk_i_BUFGP/N3" is sourceless and has been removed.
|
|
Unused block "pclk_i_BUFGP/XST_GND" (ZERO) removed.
|
|
Unused block "pclk_i_BUFGP/XST_VCC" (ONE) removed.
|
|
Unused block "sclk_i_BUFGP/XST_GND" (ZERO) removed.
|
|
Unused block "sclk_i_BUFGP/XST_VCC" (ONE) removed.
|
|
|
Optimized Block(s):
|
Optimized Block(s):
|
TYPE BLOCK
|
TYPE BLOCK
|
GND XST_GND
|
GND XST_GND
|
VCC XST_VCC
|
VCC XST_VCC
|
|
|
Redundant Block(s):
|
Redundant Block(s):
|
TYPE BLOCK
|
TYPE BLOCK
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<13>_rt
|
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<12>_rt
|
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<11>_rt
|
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<10>_rt
|
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<9>_rt
|
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<8>_rt
|
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<7>_rt
|
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<13>_rt
|
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<12>_rt
|
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<11>_rt
|
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<10>_rt
|
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<9>_rt
|
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<8>_rt
|
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<7>_rt
|
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<6>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<6>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<5>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<5>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<4>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<4>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<3>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<3>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<2>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<2>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<1>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<1>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_xor<14>_rt
|
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_xor<7>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_xor<14>_rt
|
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_xor<7>_rt
|
INV ][1211_3_INV_0
|
INV ][241_70_INV_0
|
INV ][1212_5_INV_0
|
INV ][245_78_INV_0
|
INV ][335_42_INV_0
|
INV ][249_83_INV_0
|
INV ][339_50_INV_0
|
INV ][253_88_INV_0
|
INV ][343_55_INV_0
|
INV ][257_93_INV_0
|
INV ][347_60_INV_0
|
INV ][261_98_INV_0
|
INV ][351_65_INV_0
|
INV ][269_106_INV_0
|
INV ][355_70_INV_0
|
INV ][369_161_INV_0
|
INV ][359_75_INV_0
|
INV ][373_166_INV_0
|
INV ][363_80_INV_0
|
INV ][389_179_INV_0
|
INV ][395_115_INV_0
|
INV ][397_186_INV_0
|
INV ][495_170_INV_0
|
INV ][401_190_INV_0
|
INV ][496_174_INV_0
|
INV ][402_194_INV_0
|
INV ][499_176_INV_0
|
INV ][405_196_INV_0
|
INV ][515_193_INV_0
|
INV ][409_201_INV_0
|
INV ][523_202_INV_0
|
INV ][413_206_INV_0
|
INV ][527_207_INV_0
|
INV ][417_211_INV_0
|
INV ][528_211_INV_0
|
INV ][421_216_INV_0
|
INV ][531_213_INV_0
|
INV ][425_221_INV_0
|
INV ][535_218_INV_0
|
INV ][429_226_INV_0
|
INV ][539_223_INV_0
|
INV ][453_249_INV_0
|
INV ][543_228_INV_0
|
INV ][461_256_INV_0
|
INV ][547_233_INV_0
|
INV ][465_260_INV_0
|
INV ][551_238_INV_0
|
INV ][469_264_INV_0
|
INV ][555_243_INV_0
|
INV ][645_373_INV_0
|
INV ][563_253_INV_0
|
INV ][649_378_INV_0
|
INV ][567_257_INV_0
|
INV ][653_382_INV_0
|
INV ][575_264_INV_0
|
INV ][657_386_INV_0
|
INV ][579_268_INV_0
|
INV ][661_390_INV_0
|
INV ][583_272_INV_0
|
INV ][665_394_INV_0
|
INV ][587_276_INV_0
|
INV ][669_398_INV_0
|
INV ][591_280_INV_0
|
INV ][673_402_INV_0
|
INV ][595_284_INV_0
|
INV ][694_417_INV_0
|
INV ][771_395_INV_0
|
INV ][725_439_INV_0
|
INV ][775_400_INV_0
|
INV ][729_444_INV_0
|
INV ][779_404_INV_0
|
INV ][803_502_INV_0
|
INV ][783_408_INV_0
|
INV ][836_526_INV_0
|
INV ][787_412_INV_0
|
INV ][841_529_INV_0
|
INV ][791_416_INV_0
|
INV ][878_552_INV_0
|
INV ][795_420_INV_0
|
INV ][881_556_INV_0
|
INV ][799_424_INV_0
|
INV ][918_585_INV_0
|
INV ][820_439_INV_0
|
INV ][921_589_INV_0
|
INV ][825_443_INV_0
|
INV ][927_596_INV_0
|
INV ][855_466_INV_0
|
INV ][930_600_INV_0
|
INV ][859_471_INV_0
|
|
INV ][909_508_INV_0
|
|
INV ][917_517_INV_0
|
|
INV ][921_521_INV_0
|
|
INV ][925_527_INV_0
|
|
INV ][933_533_INV_0
|
|
INV ][966_562_INV_0
|
|
INV ][971_565_INV_0
|
|
INV ][1008_588_INV_0
|
|
INV ][1011_592_INV_0
|
|
INV ][1014_596_INV_0
|
|
INV ][1042_616_INV_0
|
|
INV ][1051_628_INV_0
|
|
INV ][1054_632_INV_0
|
|
INV ][1057_636_INV_0
|
|
|
|
Section 6 - IOB Properties
|
Section 6 - IOB Properties
|
--------------------------
|
--------------------------
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
Line 290... |
Line 267... |
| dbg_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| dbg_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| dbg_o<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| dbg_o<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| dbg_o<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| dbg_o<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| dbg_o<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| dbg_o<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| dbg_o<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| dbg_o<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| gclk_i | IOB | INPUT | LVCMOS25 | | | | | | |
|
|
| led_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| led_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| led_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| led_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| led_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| led_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| led_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| led_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| led_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| led_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
Line 311... |
Line 287... |
| m_do_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| m_do_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| m_state_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| m_state_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| m_state_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| m_state_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| m_state_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| m_state_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| m_state_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| m_state_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
|
| pclk_i | IOB | INPUT | LVCMOS25 | | | | | | |
|
| s_do_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_do_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_do_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_do_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_do_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_do_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_do_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_do_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_do_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_do_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
Line 323... |
Line 300... |
| s_do_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_do_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_state_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_state_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_state_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_state_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_state_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_state_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_state_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| s_state_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
|
| sclk_i | IOB | INPUT | LVCMOS25 | | | | | | |
|
| spi_miso_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| spi_miso_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| spi_mosi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| spi_mosi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| spi_sck_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| spi_sck_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| spi_ssel_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| spi_ssel_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
| sw_i<0> | IOB | INPUT | LVCMOS25 | | | | | | |
|
| sw_i<0> | IOB | INPUT | LVCMOS25 | | | | | | |
|
Line 382... |
Line 360... |
------------------------------------
|
------------------------------------
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
| Clock Signal | Reset Signal | Set Signal | Enable Signal | Slice Load Count | Bel Load Count |
|
| Clock Signal | Reset Signal | Set Signal | Enable Signal | Slice Load Count | Bel Load Count |
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
| Inst_spi_master_port/spi_clk_reg_BUFG | | | | 6 | 11 |
|
| Inst_spi_master_port/spi_clk_reg_BUFG | | | | 6 | 11 |
|
| Inst_spi_master_port/spi_clk_reg_BUFG | | | lut1117_506 | 3 | 8 |
|
| Inst_spi_master_port/spi_clk_reg_BUFG | | | lut1157_481 | 2 | 8 |
|
| Inst_spi_master_port/spi_clk_reg_BUFG | ][1209_0 | | | 2 | 2 |
|
| Inst_spi_master_port/spi_clk_reg_BUFG | ][1041_0 | | | 2 | 2 |
|
| Inst_spi_master_port/spi_clk_reg_BUFG | ][IN_virtPIBox_574_736 | | | 1 | 2 |
|
| Inst_spi_master_port/spi_clk_reg_BUFG | ][IN_virtPIBox_541_658 | | | 1 | 2 |
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
| gclk_i_BUFGP | | | | 36 | 85 |
|
| pclk_i_BUFGP | | | | 28 | 67 |
|
| gclk_i_BUFGP | | | GLOBAL_LOGIC1 | 1 | 4 |
|
| pclk_i_BUFGP | | | GLOBAL_LOGIC1 | 1 | 4 |
|
| gclk_i_BUFGP | | | ][336_48 | 2 | 8 |
|
| pclk_i_BUFGP | | | ][210_33 | 1 | 8 |
|
| gclk_i_BUFGP | | | ][496_174 | 2 | 8 |
|
| pclk_i_BUFGP | | | ][242_76 | 2 | 6 |
|
| gclk_i_BUFGP | | | ][528_211 | 2 | 8 |
|
| pclk_i_BUFGP | | | ][402_194 | 2 | 8 |
|
| gclk_i_BUFGP | | | ][817_437 | 3 | 4 |
|
| pclk_i_BUFGP | | | lut410_104 | 1 | 2 |
|
| gclk_i_BUFGP | | | lut263_47 | 2 | 6 |
|
| pclk_i_BUFGP | | | lut422_111 | 2 | 8 |
|
| gclk_i_BUFGP | | | lut350_113 | 1 | 2 |
|
| pclk_i_BUFGP | | | lut463_128 | 2 | 8 |
|
| gclk_i_BUFGP | | | lut362_120 | 2 | 8 |
|
| pclk_i_BUFGP | | | lut504_145 | 2 | 8 |
|
| gclk_i_BUFGP | | | lut403_137 | 2 | 8 |
|
| pclk_i_BUFGP | | | lut546_164 | 2 | 8 |
|
| gclk_i_BUFGP | | | lut444_154 | 2 | 8 |
|
| pclk_i_BUFGP | | | lut710_270 | 2 | 8 |
|
| gclk_i_BUFGP | | | lut649_291 | 2 | 8 |
|
| pclk_i_BUFGP | | | lut832_320 | 2 | 6 |
|
| gclk_i_BUFGP | | | lut772_342 | 2 | 6 |
|
| pclk_i_BUFGP | | | spi_wren_reg_m | 1 | 8 |
|
| gclk_i_BUFGP | | | lut863_379 | 2 | 8 |
|
| pclk_i_BUFGP | | | spi_wren_reg_s | 1 | 2 |
|
| gclk_i_BUFGP | | | lut905_398 | 3 | 8 |
|
| pclk_i_BUFGP | ][1041_0 | | | 2 | 6 |
|
| gclk_i_BUFGP | | | spi_wren_reg_m | 2 | 8 |
|
| pclk_i_BUFGP | clear | | | 2 | 4 |
|
| gclk_i_BUFGP | | | spi_wren_reg_s | 1 | 2 |
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
| gclk_i_BUFGP | ][1209_0 | | | 2 | 6 |
|
| sclk_i_BUFGP | | | | 3 | 4 |
|
| gclk_i_BUFGP | clear | | | 2 | 4 |
|
| sclk_i_BUFGP | | | ][691_415 | 3 | 4 |
|
| gclk_i_BUFGP | spi_rst_reg | | ][817_437 | 1 | 4 |
|
| sclk_i_BUFGP | | | lut923_357 | 2 | 8 |
|
|
| sclk_i_BUFGP | | | lut965_376 | 2 | 8 |
|
|
| sclk_i_BUFGP | spi_rst_reg | | ][691_415 | 1 | 4 |
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
| ~Inst_spi_master_port/spi_clk_reg_BUFG | | | | 1 | 1 |
|
| ~Inst_spi_master_port/spi_clk_reg_BUFG | | | | 1 | 1 |
|
| ~Inst_spi_master_port/spi_clk_reg_BUFG | ][1209_0 | | | 1 | 1 |
|
| ~Inst_spi_master_port/spi_clk_reg_BUFG | ][1041_0 | | | 1 | 1 |
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
|
|
Section 13 - Utilization by Hierarchy
|
Section 13 - Utilization by Hierarchy
|
-------------------------------------
|
-------------------------------------
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical Name |
|
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical Name |
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| spi_master_atlys_top/ | | 68/139 | 71/224 | 135/145 | 0/4 | 0/0 | 0/0 | 1/2 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top |
|
| spi_master_atlys_top/ | | 65/122 | 71/210 | 111/121 | 0/4 | 0/0 | 0/0 | 2/3 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top |
|
| +Inst_btn_debouncer | | 14/14 | 33/33 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_btn_debouncer |
|
| +Inst_btn_debouncer | | 9/9 | 26/26 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_btn_debouncer |
|
| +Inst_spi_master_port | | 21/21 | 45/45 | 2/2 | 2/2 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_master_port |
|
| +Inst_spi_master_port | | 18/18 | 45/45 | 2/2 | 2/2 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_master_port |
|
| +Inst_spi_slave_port | | 23/23 | 36/36 | 6/6 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_slave_port |
|
| +Inst_spi_slave_port | | 20/20 | 36/36 | 6/6 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_slave_port |
|
| +Inst_sw_debouncer | | 13/13 | 39/39 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_sw_debouncer |
|
| +Inst_sw_debouncer | | 10/10 | 32/32 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_sw_debouncer |
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
* Slices can be packed with basic elements from multiple hierarchies.
|
* Slices can be packed with basic elements from multiple hierarchies.
|
Therefore, a slice will be counted in every hierarchical module
|
Therefore, a slice will be counted in every hierarchical module
|
that each of its packed basic elements belong to.
|
that each of its packed basic elements belong to.
|