| Line 125... |
Line 125... |
-- data. The fix consists in engaging continuous transfer regardless of the user strobing write enable, and
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-- data. The fix consists in engaging continuous transfer regardless of the user strobing write enable, and
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-- sequencing from state 1 to N as long as the master clock is present. If the user does not write new
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-- sequencing from state 1 to N as long as the master clock is present. If the user does not write new
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-- data, the last data word is repeated.
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-- data, the last data word is repeated.
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-- 2011/08/08 v2.02.0123 [JD] ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word,
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-- 2011/08/08 v2.02.0123 [JD] ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word,
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-- the slave will send (others => '0') instead.
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-- the slave will send (others => '0') instead.
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--
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-- 2011/08/28 v2.02.0126 [JD] ISSUE: the miso_o MUX that preloads tx_bit when slave is desselected will glitch for CPHA='1'.
|
|
-- FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update.
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--
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--
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-----------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------
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-- TODO
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-- TODO
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-- ====
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-- ====
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--
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--
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| Line 172... |
Line 173... |
-- There are several output ports that are used to simulate and verify the core operation.
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-- There are several output ports that are used to simulate and verify the core operation.
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-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
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-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
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-- circuitry.
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-- circuitry.
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-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
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-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
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-- synthesis tool will remove the receive logic from the generated circuitry.
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-- synthesis tool will remove the receive logic from the generated circuitry.
|
|
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
|
|
-- integrated to your circuit.
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--================================================================================================================
|
--================================================================================================================
|
|
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architecture rtl of spi_slave is
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architecture rtl of spi_slave is
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-- constants to control FlipFlop synthesis
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-- constants to control FlipFlop synthesis
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constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge
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constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge
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| Line 186... |
Line 189... |
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
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-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
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-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
|
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
|
-- especially for the Spartan-6 and newer CLB architectures, where a local reset can
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-- especially for the Spartan-6 and newer CLB architectures, where a local reset can
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-- reduce the usability of the slice registers, due to the need to share the control
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-- reduce the usability of the slice registers, due to the need to share the control
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-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
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-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
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-- By using GSR for the initialization, and reducing RESET local init to the bare
|
-- By using GSR for the initialization, and reducing RESET local init to the really
|
-- essential, the model achieves better LUT/FF packing and CLB usability.
|
-- essential, the model achieves better LUT/FF packing and CLB usability.
|
------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------
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-- internal state signals for register and combinatorial stages
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-- internal state signals for register and combinatorial stages
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signal state_next : natural range N downto 0 := 0; -- state 0 is idle state
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signal state_next : natural range N downto 0 := 0; -- state 0 is idle state
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signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state
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signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state
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-- shifter signals for register and combinatorial stages
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-- shifter signals for register and combinatorial stages
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signal sh_next : std_logic_vector (N-1 downto 0);
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signal sh_next : std_logic_vector (N-1 downto 0);
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signal sh_reg : std_logic_vector (N-1 downto 0);
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signal sh_reg : std_logic_vector (N-1 downto 0);
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-- mosi and miso connections
|
-- mosi and miso connections
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signal rx_bit_next : std_logic;
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signal rx_bit_next : std_logic; -- sample of MOSI input
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signal tx_bit_next : std_logic;
|
signal tx_bit_next : std_logic;
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signal tx_bit_reg : std_logic;
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signal tx_bit_reg : std_logic; -- drives MISO during sequential logic
|
|
signal preload_miso : std_logic; -- controls the MISO MUX
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-- buffered di_i data signals for register and combinatorial stages
|
-- buffered di_i data signals for register and combinatorial stages
|
signal di_reg : std_logic_vector (N-1 downto 0);
|
signal di_reg : std_logic_vector (N-1 downto 0);
|
-- internal wren_i stretcher for fsm combinatorial stage
|
-- internal wren_i stretcher for fsm combinatorial stage
|
signal wren : std_logic;
|
signal wren : std_logic;
|
signal wr_ack_next : std_logic := '0';
|
signal wr_ack_next : std_logic := '0';
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| Line 306... |
Line 310... |
--=============================================================================================
|
--=============================================================================================
|
-- fsm state and data registers change on spi SHIFT_EDGE
|
-- fsm state and data registers change on spi SHIFT_EDGE
|
core_reg_proc : process (spi_sck_i, spi_ssel_i) is
|
core_reg_proc : process (spi_sck_i, spi_ssel_i) is
|
begin
|
begin
|
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1)
|
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1)
|
|
-- state fsm register (fdr)
|
if spi_ssel_i = '1' then -- async clr
|
if spi_ssel_i = '1' then -- async clr
|
state_reg <= 0; -- state falls back to idle when slave not selected
|
state_reg <= 0; -- state falls back to idle when slave not selected
|
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers
|
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update state register
|
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock
|
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock
|
end if;
|
end if;
|
-- FFD registers clocked on SHIFT edge
|
-- FFD registers clocked on SHIFT edge
|
|
-- rtl core registers (fd)
|
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers
|
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers
|
sh_reg <= sh_next; -- core shift register
|
sh_reg <= sh_next; -- core shift register
|
do_buffer_reg <= do_buffer_next; -- registered data output
|
do_buffer_reg <= do_buffer_next; -- registered data output
|
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag
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do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag
|
di_req_reg <= di_req_next; -- input data request
|
di_req_reg <= di_req_next; -- input data request
|
wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization
|
wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization
|
end if;
|
end if;
|
|
-- FFD registers clocked on CHANGE edge and cleared on idle (spi_ssel_i = 1)
|
|
-- miso MUX preload control register (fdp)
|
|
if spi_ssel_i = '1' then -- async preset
|
|
preload_miso <= '1'; -- miso MUX sees top bit of parallel input when slave not selected
|
|
elsif spi_sck_i'event and spi_sck_i = CHANGE_EDGE then -- on CHANGE edge, change to tx_reg output
|
|
preload_miso <= spi_ssel_i; -- miso MUX sees tx_bit_reg when it is driven by SCK
|
|
end if;
|
-- FFD registers clocked on CHANGE edge
|
-- FFD registers clocked on CHANGE edge
|
|
-- tx_bit register (fd)
|
if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then
|
if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then
|
tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb
|
tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb
|
end if;
|
end if;
|
end process core_reg_proc;
|
end process core_reg_proc;
|
|
|
| Line 416... |
Line 430... |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output
|
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output
|
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output
|
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output
|
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output
|
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output
|
|
|
-----------------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------------
|
-- MISO driver process: copy next tx bit at reset
|
-- MISO driver process: preload top bit of parallel data to MOSI at reset
|
-----------------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------------
|
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit
|
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit
|
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic.
|
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic.
|
spi_miso_o_proc: process (spi_ssel_i, tx_bit_reg, tx_bit_next) is
|
spi_miso_o_proc: process (preload_miso, tx_bit_reg, di_reg) is
|
begin
|
begin
|
if spi_ssel_i = '1' then
|
if preload_miso = '1' then
|
spi_miso_o <= tx_bit_next; -- copy next => reg at reset
|
spi_miso_o <= di_reg(N-1); -- copy top bit of parallel data at reset
|
else
|
else
|
spi_miso_o <= tx_bit_reg;
|
spi_miso_o <= tx_bit_reg; -- copy top bit of shifter at sequential operation
|
end if;
|
end if;
|
end process spi_miso_o_proc;
|
end process spi_miso_o_proc;
|
|
|
--=============================================================================================
|
--=============================================================================================
|
-- DEBUG LOGIC PROCESSES
|
-- DEBUG LOGIC PROCESSES
|
