| Line 9... |
Line 9... |
--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- Description : (win1251) SPI мастер-приемник с минимальными затратами ресурсов.
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-- Description : (win1251) SPI мастер-приемник с минимальными затратами ресурсов.
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-- и возможностью выдачи shut-down посылки. Преназначено для загрузки АЦП AD747x.
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-- и возможностью выдачи shut-down посылки. Преназначено для загрузки АЦП AD747x.
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-- Может загружать настраиваемую часть SPI последовательности (кусок).
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-- Может загружать настраиваемую часть SPI последовательности (кусок).
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-- формирует последовательность вхождения и выхода из посылки сигналов nSS и SCK:
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-- формирует последовательность вхождения и выхода из посылки сигналов nSS и SCK:
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-- после посылка обозначается активным nSS('0'), на старте посылки SCK='1' полтакта
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-- посылка обозначается активным nSS('0'), на старте посылки SCK='1' полтакта
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-- загружаются биты по переднему фронту SCK, последний бит посылки неимеет заднего
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-- загружаются биты по переднему фронту SCK, последний бит посылки неимеет заднего
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-- фронта, SCK = '1' все пассивное время.
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-- фронта, SCK = '1' все пассивное время.
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|
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-- Description : SPI master-receiver minimalistic costs
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-- Description : SPI master-receiver minimalistic costs
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-- intended for loading ADC AD747x, capable produce shut-down frames.
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-- intended for loading ADC AD747x, capable produce shut-down frames.
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-- can load tunable part of frame. generate entry/exit sequences on nSS, SCK:
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-- can load tunable part of frame. generate entry/exit sequences on nSS, SCK:
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-- activate nSS='0' on frame transfer, SCK='1' for half clock cycle at frame start,
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-- activate nSS='0' on frame transfer, SCK='1' for half clock cycle at frame start,
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-- data loads on rising front SCK, last frame bit have no falling edge SCK,
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-- data loads on rising front SCK, last frame bit have no falling edge SCK,
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-- SCK='1' durung inactive period.
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-- SCK='1' durung inactive period.
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-- SDLen, SDMax:
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-- sets len of short spi sequence for poweroff purposes short (SDLen) and maximum (SDMax) length
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-- QuietLen:
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-- requred TimeOut before start
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-- Start:
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--Start lock on rising CLK, and changes ignores during transmition. if one still high after transmition
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-- ends, then new frame starts after QuietLen timeout if ContinueStart not active
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-- ContinueStart:
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-- if false then spi produce controling sequense of xfer entry and inter-frame pause
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-- else spi start new frame xfer immeidate after completing current frame
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-- ShutDown
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-- locks by high level, after Shuting down complete new SutDown sequence can be forced by Start
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-- if one activate during transmition, then it forces current frame to close if it can (beetween SDLen..SDMax bits)
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-- or generate short shutdown frame after completing current frae else
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-- Ready:
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-- rising edge of ready can be used for loading DQ data to dest.
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-- Shift:
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-- shift clock for internal data register intended to expand load logic to parallel loading registers,
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-- to make a multi chanel reciever
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-- Sleeping
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-- State of ADC power mode - is it shutdowned.
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- $Log$
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-- $Log$
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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| Line 33... |
Line 55... |
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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GENERIC(
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GENERIC(
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SPILen : positive := 16;
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SPILen : positive := 16;
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DataLen : positive := 16;
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DataLen : positive := 16;
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DataOffset : natural := 0;
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DataOffset : natural := 0;
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-- ShutDownLen sets len of short spi sequence for poweroff purposes
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SDLen : natural := 1;
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SDLen : natural := 1;
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SDMax : natural := 10;
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SDMax : natural := 10;
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-- requred TimeOut before start
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QuietLen : natural := 1
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QuietLen : natural := 1
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);
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);
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PORT
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PORT
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(
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(
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CLK : IN STD_LOGIC;
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CLK : IN STD_LOGIC;
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Start : IN STD_LOGIC;
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Start : IN STD_LOGIC;
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|
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-- if false then spi produce controling sequense of xfer entry and inter-frame pause
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-- else spi start new frame xfer immeidate after completing current frame
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ContinueStart : in STD_LOGIC := '0';
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ContinueStart : in STD_LOGIC := '0';
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ShutDown: IN STD_LOGIC;
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ShutDown: IN STD_LOGIC;
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reset : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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SDI : IN STD_LOGIC;
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SDI : IN STD_LOGIC;
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SCK : OUT STD_LOGIC;
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SCK : OUT STD_LOGIC;
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nSS : OUT STD_LOGIC;
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nSS : OUT STD_LOGIC;
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|
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DQ : OUT std_logic_vector(DataLen-1 downto 0);--STD_LOGIC_2D(Chanels-1 downto 0, DataLen-1 downto 0);
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DQ : OUT std_logic_vector(DataLen-1 downto 0);--STD_LOGIC_2D(Chanels-1 downto 0, DataLen-1 downto 0);
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-- rising edge of ready can be used for loading DQ data to dest.
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Ready : OUT STD_LOGIC;
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Ready : OUT STD_LOGIC;
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-- used to expand load logic to parallel loading registers, to make a multi chanel reciever
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Shift : OUT STD_LOGIC;
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Shift : OUT STD_LOGIC
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Sleeping : OUT STD_LOGIC
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);
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);
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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END AdcRecv;
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END AdcRecv;
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| Line 130... |
Line 146... |
elsif falling_edge(enable) then
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elsif falling_edge(enable) then
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SDDone <= SDEnough;
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SDDone <= SDEnough;
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end if;
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end if;
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end process;
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end process;
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|
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Sleeping <= SDDone;
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|
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Qsafer: if QuietLen > 1 generate
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Qsafer: if QuietLen > 1 generate
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QuietOk <= '1' when (QuietCnt >= QuietLen) else '0';
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QuietOk <= '1' when (QuietCnt >= QuietLen) else '0';
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QuietCounter: process(FSMState, reset, CLK, QuietOk) is begin
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QuietCounter: process(FSMState, reset, CLK, QuietOk) is begin
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if (reset = '1')
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if (reset = '1')
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