| Line 11... |
Line 11... |
input fli_srdy, // To ring_tap of port_ring_tap.v
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input fli_srdy, // To ring_tap of port_ring_tap.v
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input gmii_rx_clk, // To port_clocking of port_clocking.v, ...
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input gmii_rx_clk, // To port_clocking of port_clocking.v, ...
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input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v
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input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v
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input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v
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input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v
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input p2f_drdy, // To pkt_parse of pkt_parse.v
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input p2f_drdy, // To pkt_parse of pkt_parse.v
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input rarb_ack, // To ring_tap of port_ring_tap.v
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input ri_srdy, // To ring_tap of port_ring_tap.v
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input ri_srdy, // To ring_tap of port_ring_tap.v
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input ro_drdy, // To ring_tap of port_ring_tap.v
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input ro_drdy, // To ring_tap of port_ring_tap.v
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// End of automatics
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// End of automatics
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|
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output rarb_req,
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output fli_drdy, // From ring_tap of port_ring_tap.v
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output fli_drdy, // From ring_tap of port_ring_tap.v
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output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v
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output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v
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output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v
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output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v
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output [`PAR_DATA_SZ-1:0] p2f_data, // From pkt_parse of pkt_parse.v
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output [`PAR_DATA_SZ-1:0] p2f_data, // From pkt_parse of pkt_parse.v
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output p2f_srdy, // From pkt_parse of pkt_parse.v
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output p2f_srdy, // From pkt_parse of pkt_parse.v
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| Line 52... |
Line 54... |
wire pdo_srdy; // From pkt_parse of pkt_parse.v
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wire pdo_srdy; // From pkt_parse of pkt_parse.v
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wire prx_drdy; // From ring_tap of port_ring_tap.v
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wire prx_drdy; // From ring_tap of port_ring_tap.v
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wire prx_srdy; // From fifo_rx of sd_fifo_b.v
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wire prx_srdy; // From fifo_rx of sd_fifo_b.v
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wire ptx_drdy; // From dst of distributor.v
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wire ptx_drdy; // From dst of distributor.v
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wire ptx_srdy; // From fifo_tx of sd_fifo_b.v
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wire ptx_srdy; // From fifo_tx of sd_fifo_b.v
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wire rarb_req; // From ring_tap of port_ring_tap.v
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wire rttx_drdy; // From oflow of egr_oflow.v
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wire rttx_drdy; // From oflow of egr_oflow.v
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wire rttx_srdy; // From ring_tap of port_ring_tap.v
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wire rttx_srdy; // From ring_tap of port_ring_tap.v
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wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v
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wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v
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wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v
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wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v
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wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v
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wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v
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| Line 226... |
Line 229... |
.ro_srdy (ro_srdy),
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.ro_srdy (ro_srdy),
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.ro_data (ro_data[`PRW_SZ-1:0]), // Templated
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.ro_data (ro_data[`PRW_SZ-1:0]), // Templated
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.ptx_srdy (rttx_srdy), // Templated
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.ptx_srdy (rttx_srdy), // Templated
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.ptx_data (rttx_data), // Templated
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.ptx_data (rttx_data), // Templated
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.fli_drdy (fli_drdy),
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.fli_drdy (fli_drdy),
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.rarb_req (rarb_req),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.ri_srdy (ri_srdy),
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.ri_srdy (ri_srdy),
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.ri_data (ri_data[`PRW_SZ-1:0]), // Templated
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.ri_data (ri_data[`PRW_SZ-1:0]), // Templated
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.prx_srdy (prx_srdy), // Templated
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.prx_srdy (prx_srdy), // Templated
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.prx_data (prx_data), // Templated
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.prx_data (prx_data), // Templated
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.ro_drdy (ro_drdy),
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.ro_drdy (ro_drdy),
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.ptx_drdy (rttx_drdy), // Templated
|
.ptx_drdy (rttx_drdy), // Templated
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.fli_srdy (fli_srdy),
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.fli_srdy (fli_srdy),
|
.fli_data (fli_data[`NUM_PORTS-1:0]));
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.fli_data (fli_data[`NUM_PORTS-1:0]),
|
|
.rarb_ack (rarb_ack));
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|
|
/* egr_oflow AUTO_TEMPLATE
|
/* egr_oflow AUTO_TEMPLATE
|
(
|
(
|
.c_\(.*\) (rttx_\1[]),
|
.c_\(.*\) (rttx_\1[]),
|
.p_\(.*\) (ctx_\1[]),
|
.p_\(.*\) (ctx_\1[]),
|
