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https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
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Rev 19 |
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Line 23... |
module sd_fifo_b
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module sd_fifo_b
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#(parameter width=8,
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#(parameter width=8,
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parameter depth=256,
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parameter depth=256,
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parameter rd_commit=0,
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parameter rd_commit=0,
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parameter wr_commit=0,
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parameter wr_commit=0,
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parameter asz=$clog2(depth)
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parameter asz=$clog2(depth),
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parameter usz=$clog2(depth+1)
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)
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)
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(
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(
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input clk,
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input clk,
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input reset,
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input reset,
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input p_drdy,
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input p_drdy,
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input p_commit,
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input p_commit,
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input p_abort,
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input p_abort,
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output [width-1:0] p_data,
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output [width-1:0] p_data,
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output [asz:0] p_usage,
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output [usz-1:0] p_usage,
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output [asz:0] c_usage
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output [usz-1:0] c_usage
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);
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);
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wire [asz-1:0] com_rdptr; // From tail of sd_fifo_tail_b.v
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wire [asz-1:0] com_rdptr; // From tail of sd_fifo_tail_b.v
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wire [asz-1:0] com_wrptr; // From head of sd_fifo_head_b.v
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wire [asz-1:0] com_wrptr; // From head of sd_fifo_head_b.v
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wire [asz-1:0] cur_rdptr; // From tail of sd_fifo_tail_b.v
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wire [asz-1:0] cur_rdptr; // From tail of sd_fifo_tail_b.v
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wire [asz-1:0] cur_wrptr; // From head of sd_fifo_head_b.v
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wire [asz-1:0] cur_wrptr; // From head of sd_fifo_head_b.v
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wire [width-1:0] mem_rd_data;
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wire [width-1:0] mem_rd_data;
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wire mem_re; // From tail of sd_fifo_tail_b.v
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wire mem_re; // From tail of sd_fifo_tail_b.v
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wire mem_we; // From head of sd_fifo_head_b.v
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wire mem_we; // From head of sd_fifo_head_b.v
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wire [asz:0] usage; // From tail of sd_fifo_tail_b.v
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wire [asz-1:0] bound_high;
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wire [asz-1:0] bound_high;
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assign bound_high = depth-1;
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assign bound_high = depth-1;
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sd_fifo_head_b #(depth, wr_commit) head
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sd_fifo_head_b #(depth, wr_commit) head
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