| Line 1... |
Line 1... |
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
// Srdy/Drdy FIFO Head "B"
|
// Srdy/Drdy FIFO Head "B"
|
//
|
//
|
// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs
|
// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs
|
// based around memories, with sizes that may not be a power of 2.
|
// based around memories, with sizes that may not be a power of 2. This
|
|
// FIFO has a limitation that at most (depth-1) entries may be used.
|
//
|
//
|
// The bound inputs allow multiple FIFO controllers to share a single
|
// The bound inputs allow multiple FIFO controllers to share a single
|
// memory. The enable input is for arbitration between multiple FIFO
|
// memory. The enable input is for arbitration between multiple FIFO
|
// controllers, or between the fifo head and tail controllers on a
|
// controllers, or between the fifo head and tail controllers on a
|
// single port memory.
|
// single port memory.
|
| Line 52... |
Line 53... |
reg [asz-1:0] wrptr_p1;
|
reg [asz-1:0] wrptr_p1;
|
reg empty;
|
reg empty;
|
reg full, nxt_full;
|
reg full, nxt_full;
|
reg [asz-1:0] nxt_com_wrptr;
|
reg [asz-1:0] nxt_com_wrptr;
|
|
|
assign c_drdy = !full & enable;
|
assign c_drdy = !nxt_full & enable;
|
|
|
always @*
|
always @*
|
begin
|
begin
|
if (cur_wrptr[asz-1:0] == bound_high)
|
if (cur_wrptr[asz-1:0] == bound_high)
|
begin
|
begin
|
wrptr_p1[asz-1:0] = bound_low;
|
wrptr_p1[asz-1:0] = bound_low;
|
end
|
end
|
else
|
else
|
wrptr_p1 = cur_wrptr + 1;
|
wrptr_p1 = cur_wrptr + 1;
|
|
|
empty = (cur_wrptr == rdptr) & !full;
|
//empty = (cur_wrptr == rdptr) & !full;
|
nxt_full = ((wrptr_p1 == rdptr) | (full & (cur_wrptr == rdptr)));
|
empty = (cur_wrptr == rdptr);
|
|
|
|
// special-case -- if we do abort on a full FIFO
|
|
// force full flag to clear
|
|
/* -----\/----- EXCLUDED -----\/-----
|
|
if ((commit == 1) && c_abort && full)
|
|
nxt_full = 0;
|
|
else
|
|
nxt_full = ( (!full & (wrptr_p1 == rdptr)) | (full & (cur_wrptr == rdptr)));
|
|
-----/\----- EXCLUDED -----/\----- */
|
|
nxt_full = (wrptr_p1 == rdptr);
|
|
|
if ((commit == 1) && c_abort)
|
if ((commit == 1) && c_abort)
|
begin
|
begin
|
nxt_wrptr = com_wrptr;
|
nxt_wrptr = com_wrptr;
|
end
|
end
|
else if (enable & c_srdy & !full)
|
else if (enable & c_srdy & !nxt_full)
|
begin
|
begin
|
nxt_wrptr = wrptr_p1;
|
nxt_wrptr = wrptr_p1;
|
mem_we = 1;
|
mem_we = 1;
|
end
|
end
|
else
|
else
|
| Line 101... |
Line 112... |
generate
|
generate
|
if (commit)
|
if (commit)
|
begin
|
begin
|
always @*
|
always @*
|
begin
|
begin
|
if (enable & c_commit & !c_abort & c_srdy & !full)
|
if (enable & c_commit & !c_abort & c_srdy & !nxt_full)
|
nxt_com_wrptr = wrptr_p1;
|
nxt_com_wrptr = wrptr_p1;
|
else
|
else
|
nxt_com_wrptr = com_wrptr;
|
nxt_com_wrptr = com_wrptr;
|
end
|
end
|
|
|
