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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_head_b.v] - Diff between revs 14 and 16

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Rev 14	Rev 16
Line 27...	Line 27...
`endif	`endif

`module sd_fifo_head_b`	`module sd_fifo_head_b`
`#(parameter depth=16,`	`#(parameter depth=16,`
`parameter commit=0,`	`parameter commit=0,`
`parameter asz=$clog2(depth)`	`parameter asz=$clog2(depth),`
	`parameter usz=$clog2(depth+1)`
`)`	`)`
`(`	`(`
`input clk,`	`input clk,`
`input reset,`	`input reset,`
`input enable,`	`input enable,`
Line 44...	Line 45...
`input [asz-1:0] bound_high,`	`input [asz-1:0] bound_high,`

`input [asz-1:0] rdptr,`	`input [asz-1:0] rdptr,`
`output reg [asz-1:0] cur_wrptr,`	`output reg [asz-1:0] cur_wrptr,`
`output reg [asz-1:0] com_wrptr,`	`output reg [asz-1:0] com_wrptr,`
	`output reg [usz-1:0] c_usage,`
`output reg mem_we`	`output reg mem_we`
`);`	`);`

`reg [asz-1:0] nxt_wrptr;`	`reg [asz-1:0] nxt_wrptr;`
`reg [asz-1:0] wrptr_p1;`	`reg [asz-1:0] wrptr_p1;`
`reg empty;`	`reg empty;`
`reg full, nxt_full;`	`reg full, nxt_full;`
`reg [asz-1:0] nxt_com_wrptr;`	`reg [asz-1:0] nxt_com_wrptr;`
	`reg [usz:0] tmp_usage;`
	`wire [usz-1:0] fifo_size;`

	`assign fifo_size = bound_high - bound_low + 1;`

`assign c_drdy = !nxt_full & enable;`	`assign c_drdy = !nxt_full & enable;`

`always @*`	`always @*`
`begin`	`begin`
Line 91...	Line 97...
`else`	`else`
`begin`	`begin`
`nxt_wrptr = cur_wrptr;`	`nxt_wrptr = cur_wrptr;`
`mem_we = 0;`	`mem_we = 0;`
`end`	`end`

	`tmp_usage = cur_wrptr[asz-1:0] - rdptr[asz-1:0];`
	`if (~tmp_usage[usz])`
	`c_usage = tmp_usage[usz-1:0];`
	`else`
	`c_usage = fifo_size - (rdptr[asz-1:0] - cur_wrptr[asz-1:0]);`
`end`	`end`

`always @(posedge clk)`	`always @(posedge clk)`
`begin`	`begin`
`if (reset)`	`if (reset)`

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_head_b.v] - Diff between revs 14 and 16