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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_s.v] - Diff between revs 11 and 14

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Rev 11 Rev 14
Line 35... Line 35... 
 
 
 
 
     input       p_clk,
 
     input       p_clk,
 
     input       p_reset,
 
     input       p_reset,
 
     output      p_srdy,
 
     output      p_srdy,
 
     input       p_drdy,
 
     input       p_drdy,
 
     output reg [width-1:0] p_data
 
     output  [width-1:0] p_data
 
     );
 
     );
 
 
 
 
 
  localparam asz = $clog2(depth);
 
  localparam asz = $clog2(depth);
 
 
 
 
 
  reg [width-1:0]        mem [0:depth-1];
 
  reg [width-1:0]        mem [0:depth-1];
 
  wire [width-1:0]       mem_rddata;
 
  wire [width-1:0]       mem_rddata;
 
  wire                  rd_en;
 
  wire                  rd_en;
 
  wire [asz:0]           rdptr_tail, rdptr_tail_sync;
 
  wire [asz:0]           rdptr_tail, rdptr_tail_sync;
 
  wire                  wr_en;
 
  wire                  wr_en;
 
  wire [asz:0]           wrptr_head, wrptr_head_sync;
 
  wire [asz:0]           wrptr_head, wrptr_head_sync;
 
  reg                   dly_rd_en;
 
 
 
  wire [asz-1:0]         rd_addr, wr_addr;
 
  wire [asz-1:0]         rd_addr, wr_addr;
 
 
 
 
 
  always @(posedge c_clk)
 
/* -----\/----- EXCLUDED -----\/-----
 
    if (wr_en)
 
  always @(posedge c_clk)
 
      mem[wr_addr] <= `SDLIB_DELAY c_data;
 
    if (wr_en)
 
 
 
      mem[wr_addr] <= `SDLIB_DELAY c_data;
 
 
 
 
 
 
 
  assign mem_rddata = mem[rd_addr];
 
 
 
 -----/\----- EXCLUDED -----/\----- */
 
 
 
  behave2p_mem #(width, depth) mem2p
 
 
 
    (.d_out (p_data),
 
 
 
     .wr_en (wr_en),
 
 
 
     .rd_en (rd_en),
 
 
 
     .wr_clk (c_clk),
 
 
 
     .wr_addr (wr_addr),
 
 
 
     .rd_clk  (p_clk),
 
 
 
     .rd_addr (rd_addr),
 
 
 
     .d_in    (c_data));
 
 
 
 
 
  assign mem_rddata = mem[rd_addr];
 
 
 
 
 
 
 
  sd_fifo_head_s #(depth, async) head
 
  sd_fifo_head_s #(depth, async) head
 
    (
 
    (
 
     // Outputs
 
     // Outputs
 
     .c_drdy                            (c_drdy),
 
     .c_drdy                            (c_drdy),
Line 81... Line 92... 
     .clk                               (p_clk),
 
     .clk                               (p_clk),
 
     .reset                             (p_reset),
 
     .reset                             (p_reset),
 
     .wrptr_head                        (wrptr_head_sync),
 
     .wrptr_head                        (wrptr_head_sync),
 
     .p_drdy                            (p_drdy));
 
     .p_drdy                            (p_drdy));
 
 
 
 
 
  always @(posedge p_clk)
 
/* -----\/----- EXCLUDED -----\/-----
 
    begin
 
  always @(posedge p_clk)
 
      if (rd_en)
 
    begin
 
        p_data <= `SDLIB_DELAY mem_rddata;
 
      if (rd_en)
 
    end
 
        p_data <= `SDLIB_DELAY mem_rddata;
 
 
 
    end
 
 
 
 -----/\----- EXCLUDED -----/\----- */
 
 
 
 
 
  generate
 
  generate
 
    if (async)
 
    if (async)
 
      begin : gen_sync
 
      begin : gen_sync
 
        reg [asz:0] r_sync1, r_sync2;
 
        reg [asz:0] r_sync1, r_sync2;

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